1a2770b57SAnup Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2a2770b57SAnup Patel%YAML 1.2 3a2770b57SAnup Patel--- 4a2770b57SAnup Patel$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# 5a2770b57SAnup Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6a2770b57SAnup Patel 7a2770b57SAnup Pateltitle: SiFive Core Local Interruptor 8a2770b57SAnup Patel 9a2770b57SAnup Patelmaintainers: 10a2770b57SAnup Patel - Palmer Dabbelt <palmer@dabbelt.com> 11a2770b57SAnup Patel - Anup Patel <anup.patel@wdc.com> 12a2770b57SAnup Patel 13a2770b57SAnup Pateldescription: 14a2770b57SAnup Patel SiFive (and other RISC-V) SOCs include an implementation of the SiFive 15a2770b57SAnup Patel Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 16a2770b57SAnup Patel interrupts. It directly connects to the timer and inter-processor interrupt 17a2770b57SAnup Patel lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local 18a2770b57SAnup Patel interrupt controller is the parent interrupt controller for CLINT device. 19a2770b57SAnup Patel The clock frequency of CLINT is specified via "timebase-frequency" DT 20a2770b57SAnup Patel property of "/cpus" DT node. The "timebase-frequency" DT property is 21a2770b57SAnup Patel described in Documentation/devicetree/bindings/riscv/cpus.yaml 22a2770b57SAnup Patel 23a2770b57SAnup Patelproperties: 24a2770b57SAnup Patel compatible: 25a2770b57SAnup Patel items: 26c43b5718SDamien Le Moal - enum: 27c43b5718SDamien Le Moal - sifive,fu540-c000-clint 28*3234d3a1SEmil Renner Berthing - starfive,jh7100-clint 29c43b5718SDamien Le Moal - canaan,k210-clint 30a2770b57SAnup Patel - const: sifive,clint0 31a2770b57SAnup Patel 32a2770b57SAnup Patel description: 33c43b5718SDamien Le Moal Should be "<vendor>,<chip>-clint" and "sifive,clint<version>". 34a2770b57SAnup Patel Supported compatible strings are - 35a2770b57SAnup Patel "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated 36c43b5718SDamien Le Moal onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive 37c43b5718SDamien Le Moal CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and 38c43b5718SDamien Le Moal "sifive,clint0" for the SiFive CLINT v0 IP block with no chip 39c43b5718SDamien Le Moal integration tweaks. 40a2770b57SAnup Patel Please refer to sifive-blocks-ip-versioning.txt for details 41a2770b57SAnup Patel 42a2770b57SAnup Patel reg: 43a2770b57SAnup Patel maxItems: 1 44a2770b57SAnup Patel 45a2770b57SAnup Patel interrupts-extended: 46a2770b57SAnup Patel minItems: 1 47a2770b57SAnup Patel 48a2770b57SAnup PateladditionalProperties: false 49a2770b57SAnup Patel 50a2770b57SAnup Patelrequired: 51a2770b57SAnup Patel - compatible 52a2770b57SAnup Patel - reg 53a2770b57SAnup Patel - interrupts-extended 54a2770b57SAnup Patel 55a2770b57SAnup Patelexamples: 56a2770b57SAnup Patel - | 57a2770b57SAnup Patel timer@2000000 { 58a2770b57SAnup Patel compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 59a2770b57SAnup Patel interrupts-extended = <&cpu1intc 3 &cpu1intc 7 60a2770b57SAnup Patel &cpu2intc 3 &cpu2intc 7 61a2770b57SAnup Patel &cpu3intc 3 &cpu3intc 7 62a2770b57SAnup Patel &cpu4intc 3 &cpu4intc 7>; 63a2770b57SAnup Patel reg = <0x2000000 0x10000>; 64a2770b57SAnup Patel }; 65a2770b57SAnup Patel... 66