1a2770b57SAnup Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2a2770b57SAnup Patel%YAML 1.2 3a2770b57SAnup Patel--- 4a2770b57SAnup Patel$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# 5a2770b57SAnup Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6a2770b57SAnup Patel 7a2770b57SAnup Pateltitle: SiFive Core Local Interruptor 8a2770b57SAnup Patel 9a2770b57SAnup Patelmaintainers: 10a2770b57SAnup Patel - Palmer Dabbelt <palmer@dabbelt.com> 11a2770b57SAnup Patel - Anup Patel <anup.patel@wdc.com> 12a2770b57SAnup Patel 13a2770b57SAnup Pateldescription: 14a2770b57SAnup Patel SiFive (and other RISC-V) SOCs include an implementation of the SiFive 15a2770b57SAnup Patel Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 16a2770b57SAnup Patel interrupts. It directly connects to the timer and inter-processor interrupt 17a2770b57SAnup Patel lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local 18a2770b57SAnup Patel interrupt controller is the parent interrupt controller for CLINT device. 19a2770b57SAnup Patel The clock frequency of CLINT is specified via "timebase-frequency" DT 20a2770b57SAnup Patel property of "/cpus" DT node. The "timebase-frequency" DT property is 21a2770b57SAnup Patel described in Documentation/devicetree/bindings/riscv/cpus.yaml 22a2770b57SAnup Patel 23abd873afSIcenowy Zheng T-Head C906/C910 CPU cores include an implementation of CLINT too, however 24abd873afSIcenowy Zheng their implementation lacks a memory-mapped MTIME register, thus not 25abd873afSIcenowy Zheng compatible with SiFive ones. 26abd873afSIcenowy Zheng 27a2770b57SAnup Patelproperties: 28a2770b57SAnup Patel compatible: 2982624994SConor Dooley oneOf: 3082624994SConor Dooley - items: 31c43b5718SDamien Le Moal - enum: 32*1bd2339dSGeert Uytterhoeven - canaan,k210-clint # Canaan Kendryte K210 33*1bd2339dSGeert Uytterhoeven - sifive,fu540-c000-clint # SiFive FU540 34*1bd2339dSGeert Uytterhoeven - starfive,jh7100-clint # StarFive JH7100 35*1bd2339dSGeert Uytterhoeven - starfive,jh7110-clint # StarFive JH7110 36*1bd2339dSGeert Uytterhoeven - const: sifive,clint0 # SiFive CLINT v0 IP block 3782624994SConor Dooley - items: 38abd873afSIcenowy Zheng - enum: 39abd873afSIcenowy Zheng - allwinner,sun20i-d1-clint 40abd873afSIcenowy Zheng - const: thead,c900-clint 41abd873afSIcenowy Zheng - items: 4282624994SConor Dooley - const: sifive,clint0 4382624994SConor Dooley - const: riscv,clint0 4482624994SConor Dooley deprecated: true 4582624994SConor Dooley description: For the QEMU virt machine only 46a2770b57SAnup Patel 47a2770b57SAnup Patel description: 48*1bd2339dSGeert Uytterhoeven Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>" 49*1bd2339dSGeert Uytterhoeven when compatible with a SiFive CLINT. Please refer to 50*1bd2339dSGeert Uytterhoeven sifive-blocks-ip-versioning.txt for details regarding the latter. 51a2770b57SAnup Patel 52a2770b57SAnup Patel reg: 53a2770b57SAnup Patel maxItems: 1 54a2770b57SAnup Patel 55a2770b57SAnup Patel interrupts-extended: 56a2770b57SAnup Patel minItems: 1 5773b9f638SGeert Uytterhoeven maxItems: 4095 58a2770b57SAnup Patel 59a2770b57SAnup PateladditionalProperties: false 60a2770b57SAnup Patel 61a2770b57SAnup Patelrequired: 62a2770b57SAnup Patel - compatible 63a2770b57SAnup Patel - reg 64a2770b57SAnup Patel - interrupts-extended 65a2770b57SAnup Patel 66a2770b57SAnup Patelexamples: 67a2770b57SAnup Patel - | 68a2770b57SAnup Patel timer@2000000 { 69a2770b57SAnup Patel compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 704eb7b133SGeert Uytterhoeven interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, 714eb7b133SGeert Uytterhoeven <&cpu2intc 3>, <&cpu2intc 7>, 724eb7b133SGeert Uytterhoeven <&cpu3intc 3>, <&cpu3intc 7>, 734eb7b133SGeert Uytterhoeven <&cpu4intc 3>, <&cpu4intc 7>; 74a2770b57SAnup Patel reg = <0x2000000 0x10000>; 75a2770b57SAnup Patel }; 76a2770b57SAnup Patel... 77