xref: /linux/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb)
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC Multi Core Timer (MCT)
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11
12description: |+
13  The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14  global timer and CPU local timers. The global timer is a 64-bit free running
15  up-counter and can generate 4 interrupts when the counter reaches one of the
16  four preset counter values. The CPU local timers are 32-bit free running
17  down-counters and generate an interrupt when the counter expires. There is
18  one CPU local timer instantiated in MCT for every CPU in the system.
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - samsung,exynos4210-mct
25          - samsung,exynos4412-mct
26      - items:
27          - enum:
28              - axis,artpec8-mct
29              - axis,artpec9-mct
30              - google,gs101-mct
31              - samsung,exynos2200-mct-peris
32              - samsung,exynos3250-mct
33              - samsung,exynos5250-mct
34              - samsung,exynos5260-mct
35              - samsung,exynos5420-mct
36              - samsung,exynos5433-mct
37              - samsung,exynos850-mct
38              - samsung,exynos8895-mct
39              - samsung,exynos990-mct
40              - tesla,fsd-mct
41          - const: samsung,exynos4210-mct
42
43  clocks:
44    maxItems: 2
45
46  clock-names:
47    items:
48      - const: fin_pll
49      - const: mct
50
51  reg:
52    maxItems: 1
53
54  samsung,frc-shared:
55    type: boolean
56    description: |
57      Indicates that the hardware requires that this processor share the
58      free-running counter with a different (main) processor.
59
60  samsung,local-timers:
61    $ref: /schemas/types.yaml#/definitions/uint32-array
62    minItems: 1
63    maxItems: 16
64    description: |
65      List of indices of local timers usable from this processor.
66
67  interrupts:
68    description: |
69      Interrupts should be put in specific order. This is, the local timer
70      interrupts should be specified after the four global timer interrupts
71      have been specified:
72      0: Global Timer Interrupt 0
73      1: Global Timer Interrupt 1
74      2: Global Timer Interrupt 2
75      3: Global Timer Interrupt 3
76      4: Local Timer Interrupt 0
77      5: Local Timer Interrupt 1
78      6: ..
79      7: ..
80      i: Local Timer Interrupt n
81      For MCT block that uses a per-processor interrupt for local timers, such
82      as ones compatible with "samsung,exynos4412-mct", only one local timer
83      interrupt might be specified, meaning that all local timers use the same
84      per processor interrupt.
85    minItems: 5               # 4 Global + 1 local
86    maxItems: 20              # 4 Global + 16 local
87
88required:
89  - compatible
90  - clock-names
91  - clocks
92  - interrupts
93  - reg
94
95allOf:
96  - if:
97      not:
98        properties:
99          compatible:
100            contains:
101              enum:
102                - axis,artpec8-mct
103    then:
104      properties:
105        samsung,local-timers: false
106        samsung,frc-shared: false
107  - if:
108      properties:
109        compatible:
110          contains:
111            const: samsung,exynos3250-mct
112    then:
113      properties:
114        interrupts:
115          minItems: 8
116          maxItems: 8
117
118  - if:
119      properties:
120        compatible:
121          contains:
122            const: samsung,exynos5250-mct
123    then:
124      properties:
125        interrupts:
126          minItems: 6
127          maxItems: 6
128
129  - if:
130      properties:
131        compatible:
132          contains:
133            enum:
134              - axis,artpec8-mct
135              - axis,artpec9-mct
136              - google,gs101-mct
137              - samsung,exynos2200-mct-peris
138              - samsung,exynos5260-mct
139              - samsung,exynos5420-mct
140              - samsung,exynos5433-mct
141              - samsung,exynos850-mct
142              - samsung,exynos8895-mct
143              - samsung,exynos990-mct
144    then:
145      properties:
146        interrupts:
147          minItems: 12
148          maxItems: 12
149
150  - if:
151      properties:
152        compatible:
153          contains:
154            enum:
155              - tesla,fsd-mct
156    then:
157      properties:
158        interrupts:
159          minItems: 16
160          maxItems: 16
161
162additionalProperties: false
163
164examples:
165  - |
166    // In this example, the IP contains two local timers, using separate
167    // interrupts, so two local timer interrupts have been specified,
168    // in addition to four global timer interrupts.
169    #include <dt-bindings/clock/exynos4.h>
170    #include <dt-bindings/interrupt-controller/arm-gic.h>
171
172    timer@10050000 {
173        compatible = "samsung,exynos4210-mct";
174        reg = <0x10050000 0x800>;
175        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
176        clock-names = "fin_pll", "mct";
177
178        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
179                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
180                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
181                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
182                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
183                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
184    };
185
186  - |
187    // In this example, the timer interrupts are connected to two separate
188    // interrupt controllers. Hence, an interrupts-extended is needed.
189    #include <dt-bindings/clock/exynos4.h>
190    #include <dt-bindings/interrupt-controller/arm-gic.h>
191
192    timer@101c0000 {
193        compatible = "samsung,exynos4210-mct";
194        reg = <0x101C0000 0x800>;
195        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
196        clock-names = "fin_pll", "mct";
197
198        interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
199                              <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
200                              <&combiner 12 6>,
201                              <&combiner 12 7>,
202                              <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
203                              <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
204    };
205
206  - |
207    // In this example, the IP contains four local timers, but using
208    // a per-processor interrupt to handle them. Only one first local
209    // interrupt is specified.
210    #include <dt-bindings/clock/exynos4.h>
211    #include <dt-bindings/interrupt-controller/arm-gic.h>
212
213    timer@10050000 {
214        compatible = "samsung,exynos4412-mct";
215        reg = <0x10050000 0x800>;
216        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
217        clock-names = "fin_pll", "mct";
218
219        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
220                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
221                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
222                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
223                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
224    };
225
226  - |
227    // In this example, the IP contains four local timers, but using
228    // a per-processor interrupt to handle them. All the local timer
229    // interrupts are specified.
230    #include <dt-bindings/clock/exynos4.h>
231    #include <dt-bindings/interrupt-controller/arm-gic.h>
232
233    timer@10050000 {
234        compatible = "samsung,exynos4412-mct";
235        reg = <0x10050000 0x800>;
236        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
237        clock-names = "fin_pll", "mct";
238
239        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
240                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
241                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
242                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
243                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
244                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
245                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
246                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
247    };
248