1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung Exynos SoC Multi Core Timer (MCT) 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 12description: |+ 13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the 14 global timer and CPU local timers. The global timer is a 64-bit free running 15 up-counter and can generate 4 interrupts when the counter reaches one of the 16 four preset counter values. The CPU local timers are 32-bit free running 17 down-counters and generate an interrupt when the counter expires. There is 18 one CPU local timer instantiated in MCT for every CPU in the system. 19 20properties: 21 compatible: 22 enum: 23 - samsung,exynos4210-mct 24 - samsung,exynos4412-mct 25 26 reg: 27 maxItems: 1 28 29 interrupts: 30 description: | 31 Interrupts should be put in specific order. This is, the local timer 32 interrupts should be specified after the four global timer interrupts 33 have been specified: 34 0: Global Timer Interrupt 0 35 1: Global Timer Interrupt 1 36 2: Global Timer Interrupt 2 37 3: Global Timer Interrupt 3 38 4: Local Timer Interrupt 0 39 5: Local Timer Interrupt 1 40 6: .. 41 7: .. 42 i: Local Timer Interrupt n 43 For MCT block that uses a per-processor interrupt for local timers, such 44 as ones compatible with "samsung,exynos4412-mct", only one local timer 45 interrupt might be specified, meaning that all local timers use the same 46 per processor interrupt. 47 minItems: 5 # 4 Global + 1 local 48 maxItems: 20 # 4 Global + 16 local 49 50required: 51 - compatible 52 - interrupts 53 - reg 54 55examples: 56 - | 57 // In this example, the IP contains two local timers, using separate 58 // interrupts, so two local timer interrupts have been specified, 59 // in addition to four global timer interrupts. 60 #include <dt-bindings/interrupt-controller/arm-gic.h> 61 62 timer@10050000 { 63 compatible = "samsung,exynos4210-mct"; 64 reg = <0x10050000 0x800>; 65 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 71 }; 72 73 - | 74 // In this example, the timer interrupts are connected to two separate 75 // interrupt controllers. Hence, an interrupts-extended is needed. 76 #include <dt-bindings/interrupt-controller/arm-gic.h> 77 78 timer@101c0000 { 79 compatible = "samsung,exynos4210-mct"; 80 reg = <0x101C0000 0x800>; 81 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 82 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 83 <&combiner 12 6>, 84 <&combiner 12 7>, 85 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 86 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 87 }; 88 89 - | 90 // In this example, the IP contains four local timers, but using 91 // a per-processor interrupt to handle them. Only one first local 92 // interrupt is specified. 93 #include <dt-bindings/interrupt-controller/arm-gic.h> 94 95 timer@10050000 { 96 compatible = "samsung,exynos4412-mct"; 97 reg = <0x10050000 0x800>; 98 99 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>; 104 }; 105 106 - | 107 // In this example, the IP contains four local timers, but using 108 // a per-processor interrupt to handle them. All the local timer 109 // interrupts are specified. 110 #include <dt-bindings/interrupt-controller/arm-gic.h> 111 112 timer@10050000 { 113 compatible = "samsung,exynos4412-mct"; 114 reg = <0x10050000 0x800>; 115 116 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>; 124 }; 125