bindings/timer/riscv,timer.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V timer

maintainers:
  - Anup Patel <anup@brainfault.org>

description: |+
  RISC-V platforms always have a RISC-V timer device for the supervisor-mode
  based on the time CSR defined by the RISC-V privileged specification. The
  timer interrupts of this device are configured using the RISC-V SBI Time
  extension or the RISC-V Sstc extension.

  The clock frequency of RISC-V timer device is specified via the
  "timebase-frequency" DT property of "/cpus" DT node which is described
  in Documentation/devicetree/bindings/riscv/cpus.yaml

properties:
  compatible:
    enum:
      - riscv,timer

  interrupts-extended:
    minItems: 1
    maxItems: 4096   # Should be enough?

  riscv,timer-cannot-wake-cpu:
    type: boolean
    description:
      If present, the timer interrupt cannot wake up the CPU from one or
      more suspend/idle states.

additionalProperties: false

required:
  - compatible
  - interrupts-extended

examples:
  - |
    timer {
      compatible = "riscv,timer";
      interrupts-extended = <&cpu1intc 5>,
                            <&cpu2intc 5>,
                            <&cpu3intc 5>,
                            <&cpu4intc 5>;
    };
...