1*0c1dcfd5SSebastian HesselbarthMarvell Orion SoC timer 2*0c1dcfd5SSebastian Hesselbarth 3*0c1dcfd5SSebastian HesselbarthRequired properties: 4*0c1dcfd5SSebastian Hesselbarth- compatible: shall be "marvell,orion-timer" 5*0c1dcfd5SSebastian Hesselbarth- reg: base address of the timer register starting with TIMERS CONTROL register 6*0c1dcfd5SSebastian Hesselbarth- interrupts: should contain the interrupts for Timer0 and Timer1 7*0c1dcfd5SSebastian Hesselbarth- clocks: phandle of timer reference clock (tclk) 8*0c1dcfd5SSebastian Hesselbarth 9*0c1dcfd5SSebastian HesselbarthExample: 10*0c1dcfd5SSebastian Hesselbarth timer: timer { 11*0c1dcfd5SSebastian Hesselbarth compatible = "marvell,orion-timer"; 12*0c1dcfd5SSebastian Hesselbarth reg = <0x20300 0x20>; 13*0c1dcfd5SSebastian Hesselbarth interrupt-parent = <&bridge_intc>; 14*0c1dcfd5SSebastian Hesselbarth interrupts = <1>, <2>; 15*0c1dcfd5SSebastian Hesselbarth clocks = <&core_clk 0>; 16*0c1dcfd5SSebastian Hesselbarth }; 17