1J-Core Programmable Interval Timer and Clocksource 2 3Required properties: 4 5- compatible: Must be "jcore,pit". 6 7- reg: Memory region(s) for timer/clocksource registers. For SMP, 8 there should be one region per cpu, indexed by the sequential, 9 zero-based hardware cpu number. 10 11- interrupts: An interrupt to assign for the timer. The actual pit 12 core is integrated with the aic and allows the timer interrupt 13 assignment to be programmed by software, but this property is 14 required in order to reserve an interrupt number that doesn't 15 conflict with other devices. 16 17 18Example: 19 20timer@200 { 21 compatible = "jcore,pit"; 22 reg = < 0x200 0x30 0x500 0x30 >; 23 interrupts = < 0x48 >; 24}; 25