1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM architected timer 8 9maintainers: 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 12description: |+ 13 The per-core architected timer is expected to deliver per-CPU interrupts 14 (commonly to a GIC to deliver its per-processor interrupts as PPIs). 15 16properties: 17 compatible: 18 oneOf: 19 - items: 20 - const: arm,cortex-a15-timer 21 - const: arm,armv7-timer 22 - items: 23 - enum: 24 - arm,armv7-timer 25 - arm,armv8-timer 26 - items: 27 - const: arm,armv8-timer 28 - const: arm,armv7-timer 29 30 interrupts: 31 minItems: 2 32 items: 33 - description: EL1 secure physical timer irq, if EL3 is implemented 34 - description: EL1 non-secure physical timer irq 35 - description: EL1 virtual timer irq 36 - description: EL2 physical timer irq, if EL2 is implemented 37 - description: EL2 virtual timer irq, if FEAT_VHE is implemented 38 39 interrupt-names: 40 oneOf: 41 - minItems: 2 42 items: 43 - const: phys 44 - const: virt 45 - const: hyp-phys 46 - const: hyp-virt 47 - minItems: 3 48 items: 49 - const: sec-phys 50 - const: phys 51 - const: virt 52 - const: hyp-phys 53 - const: hyp-virt 54 55 clock-frequency: 56 description: The frequency of the main counter, in Hz. Should be present 57 only where necessary to work around broken firmware which does not configure 58 CNTFRQ on all CPUs to a uniform correct value. Use of this property is 59 strongly discouraged; fix your firmware unless absolutely impossible. 60 61 always-on: 62 type: boolean 63 description: If present, the timer is powered through an always-on power 64 domain, therefore it never loses context. 65 66 allwinner,erratum-unknown1: 67 type: boolean 68 description: Indicates the presence of an erratum found in Allwinner SoCs, 69 where reading certain values from the counter is unreliable. This also 70 affects writes to the tval register, due to the implicit counter read. 71 72 fsl,erratum-a008585: 73 type: boolean 74 description: Indicates the presence of QorIQ erratum A-008585, which says 75 that reading the counter is unreliable unless the same value is returned 76 by back-to-back reads. This also affects writes to the tval register, due 77 to the implicit counter read. 78 79 hisilicon,erratum-161010101: 80 type: boolean 81 description: Indicates the presence of Hisilicon erratum 161010101, which 82 says that reading the counters is unreliable in some cases, and reads may 83 return a value 32 beyond the correct value. This also affects writes to 84 the tval registers, due to the implicit counter read. 85 86 arm,cpu-registers-not-fw-configured: 87 type: boolean 88 description: Firmware does not initialize any of the generic timer CPU 89 registers, which contain their architecturally-defined reset values. Only 90 supported for 32-bit systems which follow the ARMv7 architected reset 91 values. 92 93 arm,no-tick-in-suspend: 94 type: boolean 95 description: The main counter does not tick when the system is in 96 low-power system suspend on some SoCs. This behavior does not match the 97 Architecture Reference Manual's specification that the system counter "must 98 be implemented in an always-on power domain." 99 100required: 101 - compatible 102 103additionalProperties: false 104 105oneOf: 106 - required: 107 - interrupts 108 - required: 109 - interrupts-extended 110 111examples: 112 - | 113 timer { 114 compatible = "arm,cortex-a15-timer", 115 "arm,armv7-timer"; 116 interrupts = <1 13 0xf08>, 117 <1 14 0xf08>, 118 <1 11 0xf08>, 119 <1 10 0xf08>; 120 clock-frequency = <100000000>; 121 }; 122 123... 124