1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm8960 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 - qcom,msm8960-tsens 27 28 - description: v0.1 of TSENS 29 items: 30 - enum: 31 - qcom,mdm9607-tsens 32 - qcom,msm8226-tsens 33 - qcom,msm8909-tsens 34 - qcom,msm8916-tsens 35 - qcom,msm8939-tsens 36 - qcom,msm8974-tsens 37 - const: qcom,tsens-v0_1 38 39 - description: v1 of TSENS 40 items: 41 - enum: 42 - qcom,msm8937-tsens 43 - qcom,msm8956-tsens 44 - qcom,msm8976-tsens 45 - qcom,qcs404-tsens 46 - const: qcom,tsens-v1 47 48 - description: v2 of TSENS 49 items: 50 - enum: 51 - qcom,msm8953-tsens 52 - qcom,msm8996-tsens 53 - qcom,msm8998-tsens 54 - qcom,qcm2290-tsens 55 - qcom,sa8255p-tsens 56 - qcom,sa8775p-tsens 57 - qcom,sar2130p-tsens 58 - qcom,sc7180-tsens 59 - qcom,sc7280-tsens 60 - qcom,sc8180x-tsens 61 - qcom,sc8280xp-tsens 62 - qcom,sdm630-tsens 63 - qcom,sdm845-tsens 64 - qcom,sm6115-tsens 65 - qcom,sm6350-tsens 66 - qcom,sm6375-tsens 67 - qcom,sm8150-tsens 68 - qcom,sm8250-tsens 69 - qcom,sm8350-tsens 70 - qcom,sm8450-tsens 71 - qcom,sm8550-tsens 72 - qcom,sm8650-tsens 73 - qcom,x1e80100-tsens 74 - const: qcom,tsens-v2 75 76 - description: v2 of TSENS with combined interrupt 77 enum: 78 - qcom,ipq8074-tsens 79 80 - description: v2 of TSENS with combined interrupt 81 items: 82 - enum: 83 - qcom,ipq9574-tsens 84 - const: qcom,ipq8074-tsens 85 86 reg: 87 items: 88 - description: TM registers 89 - description: SROT registers 90 91 interrupts: 92 minItems: 1 93 maxItems: 2 94 95 interrupt-names: 96 minItems: 1 97 maxItems: 2 98 99 nvmem-cells: 100 oneOf: 101 - minItems: 1 102 maxItems: 2 103 description: 104 Reference to an nvmem node for the calibration data 105 - minItems: 5 106 maxItems: 35 107 description: | 108 Reference to nvmem cells for the calibration mode, two calibration 109 bases and two cells per each sensor 110 # special case for msm8974 / apq8084 111 - maxItems: 51 112 description: | 113 Reference to nvmem cells for the calibration mode, two calibration 114 bases and two cells per each sensor, main and backup copies, plus use_backup cell 115 116 nvmem-cell-names: 117 oneOf: 118 - minItems: 1 119 items: 120 - const: calib 121 - enum: 122 - calib_backup 123 - calib_sel 124 - minItems: 5 125 items: 126 - const: mode 127 - const: base1 128 - const: base2 129 - pattern: '^s[0-9]+_p1$' 130 - pattern: '^s[0-9]+_p2$' 131 - pattern: '^s[0-9]+_p1$' 132 - pattern: '^s[0-9]+_p2$' 133 - pattern: '^s[0-9]+_p1$' 134 - pattern: '^s[0-9]+_p2$' 135 - pattern: '^s[0-9]+_p1$' 136 - pattern: '^s[0-9]+_p2$' 137 - pattern: '^s[0-9]+_p1$' 138 - pattern: '^s[0-9]+_p2$' 139 - pattern: '^s[0-9]+_p1$' 140 - pattern: '^s[0-9]+_p2$' 141 - pattern: '^s[0-9]+_p1$' 142 - pattern: '^s[0-9]+_p2$' 143 - pattern: '^s[0-9]+_p1$' 144 - pattern: '^s[0-9]+_p2$' 145 - pattern: '^s[0-9]+_p1$' 146 - pattern: '^s[0-9]+_p2$' 147 - pattern: '^s[0-9]+_p1$' 148 - pattern: '^s[0-9]+_p2$' 149 - pattern: '^s[0-9]+_p1$' 150 - pattern: '^s[0-9]+_p2$' 151 - pattern: '^s[0-9]+_p1$' 152 - pattern: '^s[0-9]+_p2$' 153 - pattern: '^s[0-9]+_p1$' 154 - pattern: '^s[0-9]+_p2$' 155 - pattern: '^s[0-9]+_p1$' 156 - pattern: '^s[0-9]+_p2$' 157 - pattern: '^s[0-9]+_p1$' 158 - pattern: '^s[0-9]+_p2$' 159 - pattern: '^s[0-9]+_p1$' 160 - pattern: '^s[0-9]+_p2$' 161 # special case for msm8974 / apq8084 162 - items: 163 - const: mode 164 - const: base1 165 - const: base2 166 - const: use_backup 167 - const: mode_backup 168 - const: base1_backup 169 - const: base2_backup 170 - const: s0_p1 171 - const: s0_p2 172 - const: s1_p1 173 - const: s1_p2 174 - const: s2_p1 175 - const: s2_p2 176 - const: s3_p1 177 - const: s3_p2 178 - const: s4_p1 179 - const: s4_p2 180 - const: s5_p1 181 - const: s5_p2 182 - const: s6_p1 183 - const: s6_p2 184 - const: s7_p1 185 - const: s7_p2 186 - const: s8_p1 187 - const: s8_p2 188 - const: s9_p1 189 - const: s9_p2 190 - const: s10_p1 191 - const: s10_p2 192 - const: s0_p1_backup 193 - const: s0_p2_backup 194 - const: s1_p1_backup 195 - const: s1_p2_backup 196 - const: s2_p1_backup 197 - const: s2_p2_backup 198 - const: s3_p1_backup 199 - const: s3_p2_backup 200 - const: s4_p1_backup 201 - const: s4_p2_backup 202 - const: s5_p1_backup 203 - const: s5_p2_backup 204 - const: s6_p1_backup 205 - const: s6_p2_backup 206 - const: s7_p1_backup 207 - const: s7_p2_backup 208 - const: s8_p1_backup 209 - const: s8_p2_backup 210 - const: s9_p1_backup 211 - const: s9_p2_backup 212 - const: s10_p1_backup 213 - const: s10_p2_backup 214 215 "#qcom,sensors": 216 description: 217 Number of sensors enabled on this platform 218 $ref: /schemas/types.yaml#/definitions/uint32 219 minimum: 1 220 maximum: 16 221 222 "#thermal-sensor-cells": 223 const: 1 224 225required: 226 - compatible 227 - interrupts 228 - interrupt-names 229 - "#qcom,sensors" 230 231allOf: 232 - $ref: thermal-sensor.yaml# 233 234 - if: 235 properties: 236 compatible: 237 contains: 238 enum: 239 - qcom,ipq8064-tsens 240 - qcom,msm8960-tsens 241 - qcom,tsens-v0_1 242 - qcom,tsens-v1 243 then: 244 properties: 245 interrupts: 246 items: 247 - description: Combined interrupt if upper or lower threshold crossed 248 interrupt-names: 249 items: 250 - const: uplow 251 252 - if: 253 properties: 254 compatible: 255 contains: 256 const: qcom,tsens-v2 257 then: 258 properties: 259 interrupts: 260 items: 261 - description: Combined interrupt if upper or lower threshold crossed 262 - description: Interrupt if critical threshold crossed 263 interrupt-names: 264 items: 265 - const: uplow 266 - const: critical 267 268 - if: 269 properties: 270 compatible: 271 contains: 272 enum: 273 - qcom,ipq8074-tsens 274 then: 275 properties: 276 interrupts: 277 items: 278 - description: Combined interrupt if upper, lower or critical thresholds crossed 279 interrupt-names: 280 items: 281 - const: combined 282 283 - if: 284 properties: 285 compatible: 286 contains: 287 enum: 288 - qcom,ipq8074-tsens 289 - qcom,tsens-v0_1 290 - qcom,tsens-v1 291 - qcom,tsens-v2 292 293 then: 294 required: 295 - reg 296 297unevaluatedProperties: false 298 299examples: 300 - | 301 #include <dt-bindings/interrupt-controller/arm-gic.h> 302 thermal-sensor { 303 compatible = "qcom,ipq8064-tsens"; 304 305 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 306 nvmem-cell-names = "calib", "calib_backup"; 307 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-names = "uplow"; 309 310 #qcom,sensors = <11>; 311 #thermal-sensor-cells = <1>; 312 }; 313 314 - | 315 #include <dt-bindings/interrupt-controller/arm-gic.h> 316 // Example 1 (new calibration data: for pre v1 IP): 317 thermal-sensor@4a9000 { 318 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 319 reg = <0x4a9000 0x1000>, /* TM */ 320 <0x4a8000 0x1000>; /* SROT */ 321 322 nvmem-cells = <&tsens_mode>, 323 <&tsens_base1>, <&tsens_base2>, 324 <&tsens_s0_p1>, <&tsens_s0_p2>, 325 <&tsens_s1_p1>, <&tsens_s1_p2>, 326 <&tsens_s2_p1>, <&tsens_s2_p2>, 327 <&tsens_s4_p1>, <&tsens_s4_p2>, 328 <&tsens_s5_p1>, <&tsens_s5_p2>; 329 nvmem-cell-names = "mode", 330 "base1", "base2", 331 "s0_p1", "s0_p2", 332 "s1_p1", "s1_p2", 333 "s2_p1", "s2_p2", 334 "s4_p1", "s4_p2", 335 "s5_p1", "s5_p2"; 336 337 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 338 interrupt-names = "uplow"; 339 340 #qcom,sensors = <5>; 341 #thermal-sensor-cells = <1>; 342 }; 343 344 - | 345 #include <dt-bindings/interrupt-controller/arm-gic.h> 346 // Example 1 (legacy: for pre v1 IP): 347 tsens1: thermal-sensor@4a9000 { 348 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 349 reg = <0x4a9000 0x1000>, /* TM */ 350 <0x4a8000 0x1000>; /* SROT */ 351 352 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 353 nvmem-cell-names = "calib", "calib_sel"; 354 355 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 356 interrupt-names = "uplow"; 357 358 #qcom,sensors = <5>; 359 #thermal-sensor-cells = <1>; 360 }; 361 362 - | 363 #include <dt-bindings/interrupt-controller/arm-gic.h> 364 // Example 2 (for any platform containing v1 of the TSENS IP): 365 tsens2: thermal-sensor@4a9000 { 366 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 367 reg = <0x004a9000 0x1000>, /* TM */ 368 <0x004a8000 0x1000>; /* SROT */ 369 370 nvmem-cells = <&tsens_caldata>; 371 nvmem-cell-names = "calib"; 372 373 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-names = "uplow"; 375 376 #qcom,sensors = <10>; 377 #thermal-sensor-cells = <1>; 378 }; 379 380 - | 381 #include <dt-bindings/interrupt-controller/arm-gic.h> 382 // Example 3 (for any platform containing v2 of the TSENS IP): 383 tsens3: thermal-sensor@c263000 { 384 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 385 reg = <0xc263000 0x1ff>, 386 <0xc222000 0x1ff>; 387 388 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-names = "uplow", "critical"; 391 392 #qcom,sensors = <13>; 393 #thermal-sensor-cells = <1>; 394 }; 395 396 - | 397 #include <dt-bindings/interrupt-controller/arm-gic.h> 398 // Example 4 (for any IPQ8074 based SoC-s): 399 tsens4: thermal-sensor@4a9000 { 400 compatible = "qcom,ipq8074-tsens"; 401 reg = <0x4a9000 0x1000>, 402 <0x4a8000 0x1000>; 403 404 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 405 interrupt-names = "combined"; 406 407 #qcom,sensors = <16>; 408 #thermal-sensor-cells = <1>; 409 }; 410... 411