1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm8960 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 - qcom,msm8960-tsens 27 28 - description: v0.1 of TSENS 29 items: 30 - enum: 31 - qcom,mdm9607-tsens 32 - qcom,msm8226-tsens 33 - qcom,msm8909-tsens 34 - qcom,msm8916-tsens 35 - qcom,msm8939-tsens 36 - qcom,msm8974-tsens 37 - const: qcom,tsens-v0_1 38 39 - description: v1 of TSENS 40 items: 41 - enum: 42 - qcom,ipq5018-tsens 43 - qcom,msm8937-tsens 44 - qcom,msm8956-tsens 45 - qcom,msm8976-tsens 46 - qcom,qcs404-tsens 47 - const: qcom,tsens-v1 48 49 - description: v2 of TSENS 50 items: 51 - enum: 52 - qcom,glymur-tsens 53 - qcom,milos-tsens 54 - qcom,msm8953-tsens 55 - qcom,msm8996-tsens 56 - qcom,msm8998-tsens 57 - qcom,qcm2290-tsens 58 - qcom,qcs615-tsens 59 - qcom,sa8255p-tsens 60 - qcom,sa8775p-tsens 61 - qcom,sar2130p-tsens 62 - qcom,sc7180-tsens 63 - qcom,sc7280-tsens 64 - qcom,sc8180x-tsens 65 - qcom,sc8280xp-tsens 66 - qcom,sdm630-tsens 67 - qcom,sdm845-tsens 68 - qcom,sm6115-tsens 69 - qcom,sm6350-tsens 70 - qcom,sm6375-tsens 71 - qcom,sm8150-tsens 72 - qcom,sm8250-tsens 73 - qcom,sm8350-tsens 74 - qcom,sm8450-tsens 75 - qcom,sm8550-tsens 76 - qcom,sm8650-tsens 77 - qcom,x1e80100-tsens 78 - const: qcom,tsens-v2 79 80 - description: v2 of TSENS with combined interrupt 81 enum: 82 - qcom,ipq5332-tsens 83 - qcom,ipq5424-tsens 84 - qcom,ipq8074-tsens 85 86 - description: v2 of TSENS with combined interrupt 87 items: 88 - enum: 89 - qcom,ipq6018-tsens 90 - qcom,ipq9574-tsens 91 - const: qcom,ipq8074-tsens 92 93 reg: 94 items: 95 - description: TM registers 96 - description: SROT registers 97 98 interrupts: 99 minItems: 1 100 maxItems: 2 101 102 interrupt-names: 103 minItems: 1 104 maxItems: 2 105 106 nvmem-cells: 107 oneOf: 108 - minItems: 1 109 maxItems: 2 110 description: 111 Reference to an nvmem node for the calibration data 112 - minItems: 5 113 maxItems: 35 114 description: | 115 Reference to nvmem cells for the calibration mode, two calibration 116 bases and two cells per each sensor 117 # special case for msm8974 / apq8084 118 - maxItems: 51 119 description: | 120 Reference to nvmem cells for the calibration mode, two calibration 121 bases and two cells per each sensor, main and backup copies, plus use_backup cell 122 123 nvmem-cell-names: 124 oneOf: 125 - minItems: 1 126 items: 127 - const: calib 128 - enum: 129 - calib_backup 130 - calib_sel 131 - minItems: 5 132 items: 133 - const: mode 134 - const: base1 135 - const: base2 136 - pattern: '^s[0-9]+_p1$' 137 - pattern: '^s[0-9]+_p2$' 138 - pattern: '^s[0-9]+_p1$' 139 - pattern: '^s[0-9]+_p2$' 140 - pattern: '^s[0-9]+_p1$' 141 - pattern: '^s[0-9]+_p2$' 142 - pattern: '^s[0-9]+_p1$' 143 - pattern: '^s[0-9]+_p2$' 144 - pattern: '^s[0-9]+_p1$' 145 - pattern: '^s[0-9]+_p2$' 146 - pattern: '^s[0-9]+_p1$' 147 - pattern: '^s[0-9]+_p2$' 148 - pattern: '^s[0-9]+_p1$' 149 - pattern: '^s[0-9]+_p2$' 150 - pattern: '^s[0-9]+_p1$' 151 - pattern: '^s[0-9]+_p2$' 152 - pattern: '^s[0-9]+_p1$' 153 - pattern: '^s[0-9]+_p2$' 154 - pattern: '^s[0-9]+_p1$' 155 - pattern: '^s[0-9]+_p2$' 156 - pattern: '^s[0-9]+_p1$' 157 - pattern: '^s[0-9]+_p2$' 158 - pattern: '^s[0-9]+_p1$' 159 - pattern: '^s[0-9]+_p2$' 160 - pattern: '^s[0-9]+_p1$' 161 - pattern: '^s[0-9]+_p2$' 162 - pattern: '^s[0-9]+_p1$' 163 - pattern: '^s[0-9]+_p2$' 164 - pattern: '^s[0-9]+_p1$' 165 - pattern: '^s[0-9]+_p2$' 166 - pattern: '^s[0-9]+_p1$' 167 - pattern: '^s[0-9]+_p2$' 168 # special case for msm8974 / apq8084 169 - items: 170 - const: mode 171 - const: base1 172 - const: base2 173 - const: use_backup 174 - const: mode_backup 175 - const: base1_backup 176 - const: base2_backup 177 - const: s0_p1 178 - const: s0_p2 179 - const: s1_p1 180 - const: s1_p2 181 - const: s2_p1 182 - const: s2_p2 183 - const: s3_p1 184 - const: s3_p2 185 - const: s4_p1 186 - const: s4_p2 187 - const: s5_p1 188 - const: s5_p2 189 - const: s6_p1 190 - const: s6_p2 191 - const: s7_p1 192 - const: s7_p2 193 - const: s8_p1 194 - const: s8_p2 195 - const: s9_p1 196 - const: s9_p2 197 - const: s10_p1 198 - const: s10_p2 199 - const: s0_p1_backup 200 - const: s0_p2_backup 201 - const: s1_p1_backup 202 - const: s1_p2_backup 203 - const: s2_p1_backup 204 - const: s2_p2_backup 205 - const: s3_p1_backup 206 - const: s3_p2_backup 207 - const: s4_p1_backup 208 - const: s4_p2_backup 209 - const: s5_p1_backup 210 - const: s5_p2_backup 211 - const: s6_p1_backup 212 - const: s6_p2_backup 213 - const: s7_p1_backup 214 - const: s7_p2_backup 215 - const: s8_p1_backup 216 - const: s8_p2_backup 217 - const: s9_p1_backup 218 - const: s9_p2_backup 219 - const: s10_p1_backup 220 - const: s10_p2_backup 221 - minItems: 8 222 items: 223 - const: mode 224 - const: base0 225 - const: base1 226 - pattern: '^tsens_sens[0-9]+_off$' 227 - pattern: '^tsens_sens[0-9]+_off$' 228 - pattern: '^tsens_sens[0-9]+_off$' 229 - pattern: '^tsens_sens[0-9]+_off$' 230 - pattern: '^tsens_sens[0-9]+_off$' 231 - pattern: '^tsens_sens[0-9]+_off$' 232 - pattern: '^tsens_sens[0-9]+_off$' 233 234 "#qcom,sensors": 235 description: 236 Number of sensors enabled on this platform 237 $ref: /schemas/types.yaml#/definitions/uint32 238 minimum: 1 239 maximum: 16 240 241 "#thermal-sensor-cells": 242 const: 1 243 244required: 245 - compatible 246 - interrupts 247 - interrupt-names 248 - "#qcom,sensors" 249 250allOf: 251 - $ref: thermal-sensor.yaml# 252 253 - if: 254 properties: 255 compatible: 256 contains: 257 enum: 258 - qcom,ipq5018-tsens 259 - qcom,ipq8064-tsens 260 - qcom,msm8960-tsens 261 - qcom,tsens-v0_1 262 - qcom,tsens-v1 263 then: 264 properties: 265 interrupts: 266 items: 267 - description: Combined interrupt if upper or lower threshold crossed 268 interrupt-names: 269 items: 270 - const: uplow 271 272 - if: 273 properties: 274 compatible: 275 contains: 276 const: qcom,tsens-v2 277 then: 278 properties: 279 interrupts: 280 items: 281 - description: Combined interrupt if upper or lower threshold crossed 282 - description: Interrupt if critical threshold crossed 283 interrupt-names: 284 items: 285 - const: uplow 286 - const: critical 287 288 - if: 289 properties: 290 compatible: 291 contains: 292 enum: 293 - qcom,ipq5332-tsens 294 - qcom,ipq5424-tsens 295 - qcom,ipq8074-tsens 296 then: 297 properties: 298 interrupts: 299 items: 300 - description: Combined interrupt if upper, lower or critical thresholds crossed 301 interrupt-names: 302 items: 303 - const: combined 304 305 - if: 306 properties: 307 compatible: 308 contains: 309 enum: 310 - qcom,ipq5332-tsens 311 - qcom,ipq5424-tsens 312 - qcom,ipq8074-tsens 313 - qcom,tsens-v0_1 314 - qcom,tsens-v1 315 - qcom,tsens-v2 316 317 then: 318 required: 319 - reg 320 321unevaluatedProperties: false 322 323examples: 324 - | 325 #include <dt-bindings/interrupt-controller/arm-gic.h> 326 thermal-sensor { 327 compatible = "qcom,ipq8064-tsens"; 328 329 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 330 nvmem-cell-names = "calib", "calib_backup"; 331 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 332 interrupt-names = "uplow"; 333 334 #qcom,sensors = <11>; 335 #thermal-sensor-cells = <1>; 336 }; 337 338 - | 339 #include <dt-bindings/interrupt-controller/arm-gic.h> 340 // Example 1 (new calibration data: for pre v1 IP): 341 thermal-sensor@4a9000 { 342 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 343 reg = <0x4a9000 0x1000>, /* TM */ 344 <0x4a8000 0x1000>; /* SROT */ 345 346 nvmem-cells = <&tsens_mode>, 347 <&tsens_base1>, <&tsens_base2>, 348 <&tsens_s0_p1>, <&tsens_s0_p2>, 349 <&tsens_s1_p1>, <&tsens_s1_p2>, 350 <&tsens_s2_p1>, <&tsens_s2_p2>, 351 <&tsens_s4_p1>, <&tsens_s4_p2>, 352 <&tsens_s5_p1>, <&tsens_s5_p2>; 353 nvmem-cell-names = "mode", 354 "base1", "base2", 355 "s0_p1", "s0_p2", 356 "s1_p1", "s1_p2", 357 "s2_p1", "s2_p2", 358 "s4_p1", "s4_p2", 359 "s5_p1", "s5_p2"; 360 361 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-names = "uplow"; 363 364 #qcom,sensors = <5>; 365 #thermal-sensor-cells = <1>; 366 }; 367 368 - | 369 #include <dt-bindings/interrupt-controller/arm-gic.h> 370 // Example 1 (legacy: for pre v1 IP): 371 tsens1: thermal-sensor@4a9000 { 372 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 373 reg = <0x4a9000 0x1000>, /* TM */ 374 <0x4a8000 0x1000>; /* SROT */ 375 376 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 377 nvmem-cell-names = "calib", "calib_sel"; 378 379 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 380 interrupt-names = "uplow"; 381 382 #qcom,sensors = <5>; 383 #thermal-sensor-cells = <1>; 384 }; 385 386 - | 387 #include <dt-bindings/interrupt-controller/arm-gic.h> 388 // Example 2 (for any platform containing v1 of the TSENS IP): 389 tsens2: thermal-sensor@4a9000 { 390 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 391 reg = <0x004a9000 0x1000>, /* TM */ 392 <0x004a8000 0x1000>; /* SROT */ 393 394 nvmem-cells = <&tsens_caldata>; 395 nvmem-cell-names = "calib"; 396 397 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "uplow"; 399 400 #qcom,sensors = <10>; 401 #thermal-sensor-cells = <1>; 402 }; 403 404 - | 405 #include <dt-bindings/interrupt-controller/arm-gic.h> 406 // Example 3 (for any platform containing v2 of the TSENS IP): 407 tsens3: thermal-sensor@c263000 { 408 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 409 reg = <0xc263000 0x1ff>, 410 <0xc222000 0x1ff>; 411 412 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-names = "uplow", "critical"; 415 416 #qcom,sensors = <13>; 417 #thermal-sensor-cells = <1>; 418 }; 419 420 - | 421 #include <dt-bindings/interrupt-controller/arm-gic.h> 422 // Example 4 (for any IPQ8074 based SoC-s): 423 tsens4: thermal-sensor@4a9000 { 424 compatible = "qcom,ipq8074-tsens"; 425 reg = <0x4a9000 0x1000>, 426 <0x4a8000 0x1000>; 427 428 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "combined"; 430 431 #qcom,sensors = <16>; 432 #thermal-sensor-cells = <1>; 433 }; 434... 435