xref: /linux/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml (revision a4eb44a6435d6d8f9e642407a4a06f65eb90ca04) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2021 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm Limits Management Hardware(LMh)
9
10maintainers:
11  - Thara Gopinath <thara.gopinath@linaro.org>
12
13description:
14  Limits Management Hardware(LMh) is a hardware infrastructure on some
15  Qualcomm SoCs that can enforce temperature and current limits as
16  programmed by software for certain IPs like CPU.
17
18properties:
19  compatible:
20    enum:
21      - qcom,sdm845-lmh
22
23  reg:
24    items:
25      - description: core registers
26
27  interrupts:
28    maxItems: 1
29
30  '#interrupt-cells':
31    const: 1
32
33  interrupt-controller: true
34
35  cpus:
36    description:
37      phandle of the first cpu in the LMh cluster
38    $ref: /schemas/types.yaml#/definitions/phandle
39
40  qcom,lmh-temp-arm-millicelsius:
41    description:
42      An integer expressing temperature threshold at which the LMh thermal
43      FSM is engaged.
44
45  qcom,lmh-temp-low-millicelsius:
46    description:
47      An integer expressing temperature threshold at which the state machine
48      will attempt to remove frequency throttling.
49
50  qcom,lmh-temp-high-millicelsius:
51    description:
52      An integer expressing temperature threshold at which the state machine
53      will attempt to throttle the frequency.
54
55required:
56  - compatible
57  - reg
58  - interrupts
59  - '#interrupt-cells'
60  - interrupt-controller
61  - cpus
62  - qcom,lmh-temp-arm-millicelsius
63  - qcom,lmh-temp-low-millicelsius
64  - qcom,lmh-temp-high-millicelsius
65
66additionalProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/interrupt-controller/arm-gic.h>
71
72    lmh@17d70800 {
73      compatible = "qcom,sdm845-lmh";
74      reg = <0x17d70800 0x400>;
75      interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
76      cpus = <&CPU4>;
77      qcom,lmh-temp-arm-millicelsius = <65000>;
78      qcom,lmh-temp-low-millicelsius = <94500>;
79      qcom,lmh-temp-high-millicelsius = <95000>;
80      interrupt-controller;
81      #interrupt-cells = <1>;
82    };
83