1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/thermal/mediatek,thermal.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek thermal controller for on-SoC temperatures 8 9maintainers: 10 - Sascha Hauer <s.hauer@pengutronix.de> 11 12description: 13 This device does not have its own ADC, instead it directly controls the AUXADC 14 via AHB bus accesses. For this reason it needs phandles to the AUXADC. Also it 15 controls a mux in the apmixedsys register space via AHB bus accesses, so a 16 phandle to the APMIXEDSYS is also needed. 17 18allOf: 19 - $ref: thermal-sensor.yaml# 20 21properties: 22 compatible: 23 enum: 24 - mediatek,mt2701-thermal 25 - mediatek,mt2712-thermal 26 - mediatek,mt7622-thermal 27 - mediatek,mt7981-thermal 28 - mediatek,mt7986-thermal 29 - mediatek,mt8173-thermal 30 - mediatek,mt8183-thermal 31 - mediatek,mt8365-thermal 32 - mediatek,mt8516-thermal 33 34 reg: 35 maxItems: 1 36 37 interrupts: 38 maxItems: 1 39 40 clocks: 41 items: 42 - description: Main clock needed for register access 43 - description: The AUXADC clock 44 45 clock-names: 46 items: 47 - const: therm 48 - const: auxadc 49 50 mediatek,auxadc: 51 $ref: /schemas/types.yaml#/definitions/phandle 52 description: A phandle to the AUXADC which the thermal controller uses 53 54 mediatek,apmixedsys: 55 $ref: /schemas/types.yaml#/definitions/phandle 56 description: A phandle to the APMIXEDSYS controller 57 58 resets: 59 description: Reset controller controlling the thermal controller 60 61 nvmem-cells: 62 items: 63 - description: 64 NVMEM cell with EEPROMA phandle to the calibration data provided by an 65 NVMEM device. If unspecified default values shall be used. 66 67 nvmem-cell-names: 68 items: 69 - const: calibration-data 70 71required: 72 - reg 73 - interrupts 74 - clocks 75 - clock-names 76 - mediatek,auxadc 77 - mediatek,apmixedsys 78 79unevaluatedProperties: false 80 81examples: 82 - | 83 #include <dt-bindings/interrupt-controller/irq.h> 84 #include <dt-bindings/clock/mt8173-clk.h> 85 #include <dt-bindings/reset/mt8173-resets.h> 86 87 thermal@1100b000 { 88 compatible = "mediatek,mt8173-thermal"; 89 reg = <0x1100b000 0x1000>; 90 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 91 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 92 clock-names = "therm", "auxadc"; 93 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 94 mediatek,auxadc = <&auxadc>; 95 mediatek,apmixedsys = <&apmixedsys>; 96 nvmem-cells = <&thermal_calibration_data>; 97 nvmem-cell-names = "calibration-data"; 98 #thermal-sensor-cells = <1>; 99 }; 100