1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,rpm-msg-ram 38 - rockchip,rk3288-pmu-sram 39 40 reg: 41 maxItems: 1 42 43 clocks: 44 maxItems: 1 45 description: 46 A list of phandle and clock specifier pair that controls the single 47 SRAM clock. 48 49 "#address-cells": 50 const: 1 51 52 "#size-cells": 53 const: 1 54 55 ranges: 56 maxItems: 1 57 description: 58 Should translate from local addresses within the sram to bus addresses. 59 60 no-memory-wc: 61 description: 62 The flag indicating, that SRAM memory region has not to be remapped 63 as write combining. WC is used by default. 64 type: boolean 65 66patternProperties: 67 "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$": 68 type: object 69 description: 70 Each child of the sram node specifies a region of reserved memory. 71 properties: 72 compatible: 73 description: 74 Should contain a vendor specific string in the form 75 <vendor>,[<device>-]<usage> 76 contains: 77 enum: 78 - allwinner,sun4i-a10-sram-a3-a4 79 - allwinner,sun4i-a10-sram-c1 80 - allwinner,sun4i-a10-sram-d 81 - allwinner,sun9i-a80-smp-sram 82 - allwinner,sun50i-a64-sram-c 83 - amlogic,meson8-ao-arc-sram 84 - amlogic,meson8b-ao-arc-sram 85 - amlogic,meson8-smp-sram 86 - amlogic,meson8b-smp-sram 87 - amlogic,meson-gxbb-scp-shmem 88 - amlogic,meson-axg-scp-shmem 89 - arm,juno-scp-shmem 90 - arm,scmi-shmem 91 - arm,scp-shmem 92 - renesas,smp-sram 93 - rockchip,rk3066-smp-sram 94 - samsung,exynos4210-sysram 95 - samsung,exynos4210-sysram-ns 96 - socionext,milbeaut-smp-sram 97 - stericsson,u8500-esram 98 99 reg: 100 description: 101 IO mem address range, relative to the SRAM range. 102 maxItems: 1 103 104 reg-io-width: 105 description: 106 The size (in bytes) of the IO accesses that should be performed on the 107 SRAM. 108 enum: [1, 2, 4, 8] 109 110 pool: 111 description: 112 Indicates that the particular reserved SRAM area is addressable 113 and in use by another device or devices. 114 type: boolean 115 116 export: 117 description: 118 Indicates that the reserved SRAM area may be accessed outside 119 of the kernel, e.g. by bootloader or userspace. 120 type: boolean 121 122 protect-exec: 123 description: | 124 Same as 'pool' above but with the additional constraint that code 125 will be run from the region and that the memory is maintained as 126 read-only, executable during code execution. NOTE: This region must 127 be page aligned on start and end in order to properly allow 128 manipulation of the page attributes. 129 type: boolean 130 131 label: 132 description: 133 The name for the reserved partition, if omitted, the label is taken 134 from the node name excluding the unit address. 135 136 required: 137 - reg 138 139 additionalProperties: false 140 141required: 142 - compatible 143 - reg 144 145if: 146 not: 147 properties: 148 compatible: 149 contains: 150 enum: 151 - qcom,rpm-msg-ram 152 - rockchip,rk3288-pmu-sram 153then: 154 required: 155 - "#address-cells" 156 - "#size-cells" 157 - ranges 158 159additionalProperties: false 160 161examples: 162 - | 163 sram@5c000000 { 164 compatible = "mmio-sram"; 165 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 166 167 #address-cells = <1>; 168 #size-cells = <1>; 169 ranges = <0 0x5c000000 0x40000>; 170 171 smp-sram@100 { 172 reg = <0x100 0x50>; 173 }; 174 175 device-sram@1000 { 176 reg = <0x1000 0x1000>; 177 pool; 178 }; 179 180 exported-sram@20000 { 181 reg = <0x20000 0x20000>; 182 export; 183 }; 184 }; 185 186 - | 187 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 188 // of the secondary cores. Once the core gets powered up it executes the 189 // code that is residing at some specific location of the SYSRAM. 190 // 191 // Therefore reserved section sub-nodes have to be added to the mmio-sram 192 // declaration. These nodes are of two types depending upon secure or 193 // non-secure execution environment. 194 sram@2020000 { 195 compatible = "mmio-sram"; 196 reg = <0x02020000 0x54000>; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges = <0 0x02020000 0x54000>; 200 201 smp-sram@0 { 202 compatible = "samsung,exynos4210-sysram"; 203 reg = <0x0 0x1000>; 204 }; 205 206 smp-sram@53000 { 207 compatible = "samsung,exynos4210-sysram-ns"; 208 reg = <0x53000 0x1000>; 209 }; 210 }; 211 212 - | 213 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 214 // Once the core gets powered up it executes the code that is residing at a 215 // specific location. 216 // 217 // Therefore a reserved section sub-node has to be added to the mmio-sram 218 // declaration. 219 sram@d9000000 { 220 compatible = "mmio-sram"; 221 reg = <0xd9000000 0x20000>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0xd9000000 0x20000>; 225 226 smp-sram@1ff80 { 227 compatible = "amlogic,meson8b-smp-sram"; 228 reg = <0x1ff80 0x8>; 229 }; 230 }; 231 232 - | 233 sram@e63c0000 { 234 compatible = "mmio-sram"; 235 reg = <0xe63c0000 0x1000>; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 ranges = <0 0xe63c0000 0x1000>; 239 240 smp-sram@0 { 241 compatible = "renesas,smp-sram"; 242 reg = <0 0x10>; 243 }; 244 }; 245 246 - | 247 sram@10080000 { 248 compatible = "mmio-sram"; 249 reg = <0x10080000 0x10000>; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 ranges; 253 254 smp-sram@10080000 { 255 compatible = "rockchip,rk3066-smp-sram"; 256 reg = <0x10080000 0x50>; 257 }; 258 }; 259 260 - | 261 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 262 // resume from maskrom(the 1st level loader). This is a common use of 263 // the "pmu-sram" because it keeps power even in low power states 264 // in the system. 265 sram@ff720000 { 266 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 267 reg = <0xff720000 0x1000>; 268 }; 269 270 - | 271 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 272 // primary core (cpu0). Once the core gets powered up it checks if a magic 273 // value is set at a specific location. If it is then the BROM will jump 274 // to the software entry address, instead of executing a standard boot. 275 // 276 // Also there are no "secure-only" properties. The implementation should 277 // check if this SRAM is usable first. 278 sram@20000 { 279 // 256 KiB secure SRAM at 0x20000 280 compatible = "mmio-sram"; 281 reg = <0x00020000 0x40000>; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 ranges = <0 0x00020000 0x40000>; 285 286 smp-sram@1000 { 287 // This is checked by BROM to determine if 288 // cpu0 should jump to SMP entry vector 289 compatible = "allwinner,sun9i-a80-smp-sram"; 290 reg = <0x1000 0x8>; 291 }; 292 }; 293 294 - | 295 sram@0 { 296 compatible = "mmio-sram"; 297 reg = <0x0 0x10000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 ranges = <0 0x0 0x10000>; 301 302 smp-sram@f100 { 303 compatible = "socionext,milbeaut-smp-sram"; 304 reg = <0xf100 0x20>; 305 }; 306 }; 307