1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,eliza-imem 38 - qcom,glymur-imem 39 - qcom,hawi-imem 40 - qcom,kaanapali-imem 41 - qcom,milos-imem 42 - qcom,rpm-msg-ram 43 - rockchip,rk3288-pmu-sram 44 45 reg: 46 maxItems: 1 47 48 clocks: 49 maxItems: 1 50 description: 51 A list of phandle and clock specifier pair that controls the single 52 SRAM clock. 53 54 "#address-cells": 55 const: 1 56 57 "#size-cells": 58 const: 1 59 60 ranges: 61 maxItems: 1 62 description: 63 Should translate from local addresses within the sram to bus addresses. 64 65 no-memory-wc: 66 description: 67 The flag indicating, that SRAM memory region has not to be remapped 68 as write combining. WC is used by default. 69 type: boolean 70 71patternProperties: 72 "^([a-z0-9]+-)*sram(-section)?@[a-f0-9]+$": 73 type: object 74 description: 75 Each child of the sram node specifies a region of reserved memory. 76 properties: 77 compatible: 78 description: 79 Should contain a vendor specific string in the form 80 <vendor>,[<device>-]<usage> 81 contains: 82 enum: 83 - allwinner,sun4i-a10-sram-a3-a4 84 - allwinner,sun4i-a10-sram-c1 85 - allwinner,sun4i-a10-sram-d 86 - allwinner,sun9i-a80-smp-sram 87 - allwinner,sun50i-a64-sram-c 88 - allwinner,sun50i-h616-ve-sram 89 - amlogic,meson8-ao-arc-sram 90 - amlogic,meson8b-ao-arc-sram 91 - amlogic,meson8-smp-sram 92 - amlogic,meson8b-smp-sram 93 - amlogic,meson-gxbb-scp-shmem 94 - amlogic,meson-axg-scp-shmem 95 - arm,juno-scp-shmem 96 - arm,scmi-shmem 97 - arm,scp-shmem 98 - qcom,pil-reloc-info 99 - renesas,smp-sram 100 - rockchip,rk3066-smp-sram 101 - samsung,exynos4210-sysram 102 - samsung,exynos4210-sysram-ns 103 - socionext,milbeaut-smp-sram 104 - stericsson,u8500-esram 105 106 reg: 107 description: 108 IO mem address range, relative to the SRAM range. 109 maxItems: 1 110 111 reg-io-width: 112 description: 113 The size (in bytes) of the IO accesses that should be performed on the 114 SRAM. 115 enum: [1, 2, 4, 8] 116 117 pool: 118 description: 119 Indicates that the particular reserved SRAM area is addressable 120 and in use by another device or devices. 121 type: boolean 122 123 export: 124 description: 125 Indicates that the reserved SRAM area may be accessed outside 126 of the kernel, e.g. by bootloader or userspace. 127 type: boolean 128 129 protect-exec: 130 description: | 131 Same as 'pool' above but with the additional constraint that code 132 will be run from the region and that the memory is maintained as 133 read-only, executable during code execution. NOTE: This region must 134 be page aligned on start and end in order to properly allow 135 manipulation of the page attributes. 136 type: boolean 137 138 label: 139 description: 140 The name for the reserved partition, if omitted, the label is taken 141 from the node name excluding the unit address. 142 143 required: 144 - reg 145 146 additionalProperties: false 147 148required: 149 - compatible 150 - reg 151 152if: 153 not: 154 properties: 155 compatible: 156 contains: 157 enum: 158 - qcom,rpm-msg-ram 159 - rockchip,rk3288-pmu-sram 160then: 161 required: 162 - "#address-cells" 163 - "#size-cells" 164 - ranges 165 166additionalProperties: false 167 168examples: 169 - | 170 sram@5c000000 { 171 compatible = "mmio-sram"; 172 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 173 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges = <0 0x5c000000 0x40000>; 177 178 smp-sram@100 { 179 reg = <0x100 0x50>; 180 }; 181 182 device-sram@1000 { 183 reg = <0x1000 0x1000>; 184 pool; 185 }; 186 187 exported-sram@20000 { 188 reg = <0x20000 0x20000>; 189 export; 190 }; 191 }; 192 193 - | 194 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 195 // of the secondary cores. Once the core gets powered up it executes the 196 // code that is residing at some specific location of the SYSRAM. 197 // 198 // Therefore reserved section sub-nodes have to be added to the mmio-sram 199 // declaration. These nodes are of two types depending upon secure or 200 // non-secure execution environment. 201 sram@2020000 { 202 compatible = "mmio-sram"; 203 reg = <0x02020000 0x54000>; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges = <0 0x02020000 0x54000>; 207 208 smp-sram@0 { 209 compatible = "samsung,exynos4210-sysram"; 210 reg = <0x0 0x1000>; 211 }; 212 213 smp-sram@53000 { 214 compatible = "samsung,exynos4210-sysram-ns"; 215 reg = <0x53000 0x1000>; 216 }; 217 }; 218 219 - | 220 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 221 // Once the core gets powered up it executes the code that is residing at a 222 // specific location. 223 // 224 // Therefore a reserved section sub-node has to be added to the mmio-sram 225 // declaration. 226 sram@d9000000 { 227 compatible = "mmio-sram"; 228 reg = <0xd9000000 0x20000>; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 ranges = <0 0xd9000000 0x20000>; 232 233 smp-sram@1ff80 { 234 compatible = "amlogic,meson8b-smp-sram"; 235 reg = <0x1ff80 0x8>; 236 }; 237 }; 238 239 - | 240 sram@e63c0000 { 241 compatible = "mmio-sram"; 242 reg = <0xe63c0000 0x1000>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 ranges = <0 0xe63c0000 0x1000>; 246 247 smp-sram@0 { 248 compatible = "renesas,smp-sram"; 249 reg = <0 0x10>; 250 }; 251 }; 252 253 - | 254 sram@10080000 { 255 compatible = "mmio-sram"; 256 reg = <0x10080000 0x10000>; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges; 260 261 smp-sram@10080000 { 262 compatible = "rockchip,rk3066-smp-sram"; 263 reg = <0x10080000 0x50>; 264 }; 265 }; 266 267 - | 268 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 269 // resume from maskrom(the 1st level loader). This is a common use of 270 // the "pmu-sram" because it keeps power even in low power states 271 // in the system. 272 sram@ff720000 { 273 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 274 reg = <0xff720000 0x1000>; 275 }; 276 277 - | 278 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 279 // primary core (cpu0). Once the core gets powered up it checks if a magic 280 // value is set at a specific location. If it is then the BROM will jump 281 // to the software entry address, instead of executing a standard boot. 282 // 283 // Also there are no "secure-only" properties. The implementation should 284 // check if this SRAM is usable first. 285 sram@20000 { 286 // 256 KiB secure SRAM at 0x20000 287 compatible = "mmio-sram"; 288 reg = <0x00020000 0x40000>; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 ranges = <0 0x00020000 0x40000>; 292 293 smp-sram@1000 { 294 // This is checked by BROM to determine if 295 // cpu0 should jump to SMP entry vector 296 compatible = "allwinner,sun9i-a80-smp-sram"; 297 reg = <0x1000 0x8>; 298 }; 299 }; 300 301 - | 302 sram@0 { 303 compatible = "mmio-sram"; 304 reg = <0x0 0x10000>; 305 #address-cells = <1>; 306 #size-cells = <1>; 307 ranges = <0 0x0 0x10000>; 308 309 smp-sram@f100 { 310 compatible = "socionext,milbeaut-smp-sram"; 311 reg = <0xf100 0x20>; 312 }; 313 }; 314