1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,kaanapali-imem 38 - qcom,rpm-msg-ram 39 - rockchip,rk3288-pmu-sram 40 41 reg: 42 maxItems: 1 43 44 clocks: 45 maxItems: 1 46 description: 47 A list of phandle and clock specifier pair that controls the single 48 SRAM clock. 49 50 "#address-cells": 51 const: 1 52 53 "#size-cells": 54 const: 1 55 56 ranges: 57 maxItems: 1 58 description: 59 Should translate from local addresses within the sram to bus addresses. 60 61 no-memory-wc: 62 description: 63 The flag indicating, that SRAM memory region has not to be remapped 64 as write combining. WC is used by default. 65 type: boolean 66 67patternProperties: 68 "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$": 69 type: object 70 description: 71 Each child of the sram node specifies a region of reserved memory. 72 properties: 73 compatible: 74 description: 75 Should contain a vendor specific string in the form 76 <vendor>,[<device>-]<usage> 77 contains: 78 enum: 79 - allwinner,sun4i-a10-sram-a3-a4 80 - allwinner,sun4i-a10-sram-c1 81 - allwinner,sun4i-a10-sram-d 82 - allwinner,sun9i-a80-smp-sram 83 - allwinner,sun50i-a64-sram-c 84 - amlogic,meson8-ao-arc-sram 85 - amlogic,meson8b-ao-arc-sram 86 - amlogic,meson8-smp-sram 87 - amlogic,meson8b-smp-sram 88 - amlogic,meson-gxbb-scp-shmem 89 - amlogic,meson-axg-scp-shmem 90 - arm,juno-scp-shmem 91 - arm,scmi-shmem 92 - arm,scp-shmem 93 - qcom,pil-reloc-info 94 - renesas,smp-sram 95 - rockchip,rk3066-smp-sram 96 - samsung,exynos4210-sysram 97 - samsung,exynos4210-sysram-ns 98 - socionext,milbeaut-smp-sram 99 - stericsson,u8500-esram 100 101 reg: 102 description: 103 IO mem address range, relative to the SRAM range. 104 maxItems: 1 105 106 reg-io-width: 107 description: 108 The size (in bytes) of the IO accesses that should be performed on the 109 SRAM. 110 enum: [1, 2, 4, 8] 111 112 pool: 113 description: 114 Indicates that the particular reserved SRAM area is addressable 115 and in use by another device or devices. 116 type: boolean 117 118 export: 119 description: 120 Indicates that the reserved SRAM area may be accessed outside 121 of the kernel, e.g. by bootloader or userspace. 122 type: boolean 123 124 protect-exec: 125 description: | 126 Same as 'pool' above but with the additional constraint that code 127 will be run from the region and that the memory is maintained as 128 read-only, executable during code execution. NOTE: This region must 129 be page aligned on start and end in order to properly allow 130 manipulation of the page attributes. 131 type: boolean 132 133 label: 134 description: 135 The name for the reserved partition, if omitted, the label is taken 136 from the node name excluding the unit address. 137 138 required: 139 - reg 140 141 additionalProperties: false 142 143required: 144 - compatible 145 - reg 146 147if: 148 not: 149 properties: 150 compatible: 151 contains: 152 enum: 153 - qcom,rpm-msg-ram 154 - rockchip,rk3288-pmu-sram 155then: 156 required: 157 - "#address-cells" 158 - "#size-cells" 159 - ranges 160 161additionalProperties: false 162 163examples: 164 - | 165 sram@5c000000 { 166 compatible = "mmio-sram"; 167 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 168 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges = <0 0x5c000000 0x40000>; 172 173 smp-sram@100 { 174 reg = <0x100 0x50>; 175 }; 176 177 device-sram@1000 { 178 reg = <0x1000 0x1000>; 179 pool; 180 }; 181 182 exported-sram@20000 { 183 reg = <0x20000 0x20000>; 184 export; 185 }; 186 }; 187 188 - | 189 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 190 // of the secondary cores. Once the core gets powered up it executes the 191 // code that is residing at some specific location of the SYSRAM. 192 // 193 // Therefore reserved section sub-nodes have to be added to the mmio-sram 194 // declaration. These nodes are of two types depending upon secure or 195 // non-secure execution environment. 196 sram@2020000 { 197 compatible = "mmio-sram"; 198 reg = <0x02020000 0x54000>; 199 #address-cells = <1>; 200 #size-cells = <1>; 201 ranges = <0 0x02020000 0x54000>; 202 203 smp-sram@0 { 204 compatible = "samsung,exynos4210-sysram"; 205 reg = <0x0 0x1000>; 206 }; 207 208 smp-sram@53000 { 209 compatible = "samsung,exynos4210-sysram-ns"; 210 reg = <0x53000 0x1000>; 211 }; 212 }; 213 214 - | 215 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 216 // Once the core gets powered up it executes the code that is residing at a 217 // specific location. 218 // 219 // Therefore a reserved section sub-node has to be added to the mmio-sram 220 // declaration. 221 sram@d9000000 { 222 compatible = "mmio-sram"; 223 reg = <0xd9000000 0x20000>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0xd9000000 0x20000>; 227 228 smp-sram@1ff80 { 229 compatible = "amlogic,meson8b-smp-sram"; 230 reg = <0x1ff80 0x8>; 231 }; 232 }; 233 234 - | 235 sram@e63c0000 { 236 compatible = "mmio-sram"; 237 reg = <0xe63c0000 0x1000>; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 ranges = <0 0xe63c0000 0x1000>; 241 242 smp-sram@0 { 243 compatible = "renesas,smp-sram"; 244 reg = <0 0x10>; 245 }; 246 }; 247 248 - | 249 sram@10080000 { 250 compatible = "mmio-sram"; 251 reg = <0x10080000 0x10000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges; 255 256 smp-sram@10080000 { 257 compatible = "rockchip,rk3066-smp-sram"; 258 reg = <0x10080000 0x50>; 259 }; 260 }; 261 262 - | 263 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 264 // resume from maskrom(the 1st level loader). This is a common use of 265 // the "pmu-sram" because it keeps power even in low power states 266 // in the system. 267 sram@ff720000 { 268 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 269 reg = <0xff720000 0x1000>; 270 }; 271 272 - | 273 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 274 // primary core (cpu0). Once the core gets powered up it checks if a magic 275 // value is set at a specific location. If it is then the BROM will jump 276 // to the software entry address, instead of executing a standard boot. 277 // 278 // Also there are no "secure-only" properties. The implementation should 279 // check if this SRAM is usable first. 280 sram@20000 { 281 // 256 KiB secure SRAM at 0x20000 282 compatible = "mmio-sram"; 283 reg = <0x00020000 0x40000>; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 ranges = <0 0x00020000 0x40000>; 287 288 smp-sram@1000 { 289 // This is checked by BROM to determine if 290 // cpu0 should jump to SMP entry vector 291 compatible = "allwinner,sun9i-a80-smp-sram"; 292 reg = <0x1000 0x8>; 293 }; 294 }; 295 296 - | 297 sram@0 { 298 compatible = "mmio-sram"; 299 reg = <0x0 0x10000>; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 ranges = <0 0x0 0x10000>; 303 304 smp-sram@f100 { 305 compatible = "socionext,milbeaut-smp-sram"; 306 reg = <0xf100 0x20>; 307 }; 308 }; 309