1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,eliza-imem 38 - qcom,hawi-imem 39 - qcom,kaanapali-imem 40 - qcom,milos-imem 41 - qcom,rpm-msg-ram 42 - rockchip,rk3288-pmu-sram 43 44 reg: 45 maxItems: 1 46 47 clocks: 48 maxItems: 1 49 description: 50 A list of phandle and clock specifier pair that controls the single 51 SRAM clock. 52 53 "#address-cells": 54 const: 1 55 56 "#size-cells": 57 const: 1 58 59 ranges: 60 maxItems: 1 61 description: 62 Should translate from local addresses within the sram to bus addresses. 63 64 no-memory-wc: 65 description: 66 The flag indicating, that SRAM memory region has not to be remapped 67 as write combining. WC is used by default. 68 type: boolean 69 70patternProperties: 71 "^([a-z0-9]+-)*sram(-section)?@[a-f0-9]+$": 72 type: object 73 description: 74 Each child of the sram node specifies a region of reserved memory. 75 properties: 76 compatible: 77 description: 78 Should contain a vendor specific string in the form 79 <vendor>,[<device>-]<usage> 80 contains: 81 enum: 82 - allwinner,sun4i-a10-sram-a3-a4 83 - allwinner,sun4i-a10-sram-c1 84 - allwinner,sun4i-a10-sram-d 85 - allwinner,sun9i-a80-smp-sram 86 - allwinner,sun50i-a64-sram-c 87 - allwinner,sun50i-h616-ve-sram 88 - amlogic,meson8-ao-arc-sram 89 - amlogic,meson8b-ao-arc-sram 90 - amlogic,meson8-smp-sram 91 - amlogic,meson8b-smp-sram 92 - amlogic,meson-gxbb-scp-shmem 93 - amlogic,meson-axg-scp-shmem 94 - arm,juno-scp-shmem 95 - arm,scmi-shmem 96 - arm,scp-shmem 97 - qcom,pil-reloc-info 98 - renesas,smp-sram 99 - rockchip,rk3066-smp-sram 100 - samsung,exynos4210-sysram 101 - samsung,exynos4210-sysram-ns 102 - socionext,milbeaut-smp-sram 103 - stericsson,u8500-esram 104 105 reg: 106 description: 107 IO mem address range, relative to the SRAM range. 108 maxItems: 1 109 110 reg-io-width: 111 description: 112 The size (in bytes) of the IO accesses that should be performed on the 113 SRAM. 114 enum: [1, 2, 4, 8] 115 116 pool: 117 description: 118 Indicates that the particular reserved SRAM area is addressable 119 and in use by another device or devices. 120 type: boolean 121 122 export: 123 description: 124 Indicates that the reserved SRAM area may be accessed outside 125 of the kernel, e.g. by bootloader or userspace. 126 type: boolean 127 128 protect-exec: 129 description: | 130 Same as 'pool' above but with the additional constraint that code 131 will be run from the region and that the memory is maintained as 132 read-only, executable during code execution. NOTE: This region must 133 be page aligned on start and end in order to properly allow 134 manipulation of the page attributes. 135 type: boolean 136 137 label: 138 description: 139 The name for the reserved partition, if omitted, the label is taken 140 from the node name excluding the unit address. 141 142 required: 143 - reg 144 145 additionalProperties: false 146 147required: 148 - compatible 149 - reg 150 151if: 152 not: 153 properties: 154 compatible: 155 contains: 156 enum: 157 - qcom,rpm-msg-ram 158 - rockchip,rk3288-pmu-sram 159then: 160 required: 161 - "#address-cells" 162 - "#size-cells" 163 - ranges 164 165additionalProperties: false 166 167examples: 168 - | 169 sram@5c000000 { 170 compatible = "mmio-sram"; 171 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 172 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0 0x5c000000 0x40000>; 176 177 smp-sram@100 { 178 reg = <0x100 0x50>; 179 }; 180 181 device-sram@1000 { 182 reg = <0x1000 0x1000>; 183 pool; 184 }; 185 186 exported-sram@20000 { 187 reg = <0x20000 0x20000>; 188 export; 189 }; 190 }; 191 192 - | 193 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 194 // of the secondary cores. Once the core gets powered up it executes the 195 // code that is residing at some specific location of the SYSRAM. 196 // 197 // Therefore reserved section sub-nodes have to be added to the mmio-sram 198 // declaration. These nodes are of two types depending upon secure or 199 // non-secure execution environment. 200 sram@2020000 { 201 compatible = "mmio-sram"; 202 reg = <0x02020000 0x54000>; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges = <0 0x02020000 0x54000>; 206 207 smp-sram@0 { 208 compatible = "samsung,exynos4210-sysram"; 209 reg = <0x0 0x1000>; 210 }; 211 212 smp-sram@53000 { 213 compatible = "samsung,exynos4210-sysram-ns"; 214 reg = <0x53000 0x1000>; 215 }; 216 }; 217 218 - | 219 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 220 // Once the core gets powered up it executes the code that is residing at a 221 // specific location. 222 // 223 // Therefore a reserved section sub-node has to be added to the mmio-sram 224 // declaration. 225 sram@d9000000 { 226 compatible = "mmio-sram"; 227 reg = <0xd9000000 0x20000>; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges = <0 0xd9000000 0x20000>; 231 232 smp-sram@1ff80 { 233 compatible = "amlogic,meson8b-smp-sram"; 234 reg = <0x1ff80 0x8>; 235 }; 236 }; 237 238 - | 239 sram@e63c0000 { 240 compatible = "mmio-sram"; 241 reg = <0xe63c0000 0x1000>; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 ranges = <0 0xe63c0000 0x1000>; 245 246 smp-sram@0 { 247 compatible = "renesas,smp-sram"; 248 reg = <0 0x10>; 249 }; 250 }; 251 252 - | 253 sram@10080000 { 254 compatible = "mmio-sram"; 255 reg = <0x10080000 0x10000>; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 ranges; 259 260 smp-sram@10080000 { 261 compatible = "rockchip,rk3066-smp-sram"; 262 reg = <0x10080000 0x50>; 263 }; 264 }; 265 266 - | 267 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 268 // resume from maskrom(the 1st level loader). This is a common use of 269 // the "pmu-sram" because it keeps power even in low power states 270 // in the system. 271 sram@ff720000 { 272 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 273 reg = <0xff720000 0x1000>; 274 }; 275 276 - | 277 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 278 // primary core (cpu0). Once the core gets powered up it checks if a magic 279 // value is set at a specific location. If it is then the BROM will jump 280 // to the software entry address, instead of executing a standard boot. 281 // 282 // Also there are no "secure-only" properties. The implementation should 283 // check if this SRAM is usable first. 284 sram@20000 { 285 // 256 KiB secure SRAM at 0x20000 286 compatible = "mmio-sram"; 287 reg = <0x00020000 0x40000>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges = <0 0x00020000 0x40000>; 291 292 smp-sram@1000 { 293 // This is checked by BROM to determine if 294 // cpu0 should jump to SMP entry vector 295 compatible = "allwinner,sun9i-a80-smp-sram"; 296 reg = <0x1000 0x8>; 297 }; 298 }; 299 300 - | 301 sram@0 { 302 compatible = "mmio-sram"; 303 reg = <0x0 0x10000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges = <0 0x0 0x10000>; 307 308 smp-sram@f100 { 309 compatible = "socionext,milbeaut-smp-sram"; 310 reg = <0xf100 0x20>; 311 }; 312 }; 313