1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,hawi-imem 38 - qcom,kaanapali-imem 39 - qcom,milos-imem 40 - qcom,rpm-msg-ram 41 - rockchip,rk3288-pmu-sram 42 43 reg: 44 maxItems: 1 45 46 clocks: 47 maxItems: 1 48 description: 49 A list of phandle and clock specifier pair that controls the single 50 SRAM clock. 51 52 "#address-cells": 53 const: 1 54 55 "#size-cells": 56 const: 1 57 58 ranges: 59 maxItems: 1 60 description: 61 Should translate from local addresses within the sram to bus addresses. 62 63 no-memory-wc: 64 description: 65 The flag indicating, that SRAM memory region has not to be remapped 66 as write combining. WC is used by default. 67 type: boolean 68 69patternProperties: 70 "^([a-z0-9]+-)*sram(-section)?@[a-f0-9]+$": 71 type: object 72 description: 73 Each child of the sram node specifies a region of reserved memory. 74 properties: 75 compatible: 76 description: 77 Should contain a vendor specific string in the form 78 <vendor>,[<device>-]<usage> 79 contains: 80 enum: 81 - allwinner,sun4i-a10-sram-a3-a4 82 - allwinner,sun4i-a10-sram-c1 83 - allwinner,sun4i-a10-sram-d 84 - allwinner,sun9i-a80-smp-sram 85 - allwinner,sun50i-a64-sram-c 86 - amlogic,meson8-ao-arc-sram 87 - amlogic,meson8b-ao-arc-sram 88 - amlogic,meson8-smp-sram 89 - amlogic,meson8b-smp-sram 90 - amlogic,meson-gxbb-scp-shmem 91 - amlogic,meson-axg-scp-shmem 92 - arm,juno-scp-shmem 93 - arm,scmi-shmem 94 - arm,scp-shmem 95 - qcom,pil-reloc-info 96 - renesas,smp-sram 97 - rockchip,rk3066-smp-sram 98 - samsung,exynos4210-sysram 99 - samsung,exynos4210-sysram-ns 100 - socionext,milbeaut-smp-sram 101 - stericsson,u8500-esram 102 103 reg: 104 description: 105 IO mem address range, relative to the SRAM range. 106 maxItems: 1 107 108 reg-io-width: 109 description: 110 The size (in bytes) of the IO accesses that should be performed on the 111 SRAM. 112 enum: [1, 2, 4, 8] 113 114 pool: 115 description: 116 Indicates that the particular reserved SRAM area is addressable 117 and in use by another device or devices. 118 type: boolean 119 120 export: 121 description: 122 Indicates that the reserved SRAM area may be accessed outside 123 of the kernel, e.g. by bootloader or userspace. 124 type: boolean 125 126 protect-exec: 127 description: | 128 Same as 'pool' above but with the additional constraint that code 129 will be run from the region and that the memory is maintained as 130 read-only, executable during code execution. NOTE: This region must 131 be page aligned on start and end in order to properly allow 132 manipulation of the page attributes. 133 type: boolean 134 135 label: 136 description: 137 The name for the reserved partition, if omitted, the label is taken 138 from the node name excluding the unit address. 139 140 required: 141 - reg 142 143 additionalProperties: false 144 145required: 146 - compatible 147 - reg 148 149if: 150 not: 151 properties: 152 compatible: 153 contains: 154 enum: 155 - qcom,rpm-msg-ram 156 - rockchip,rk3288-pmu-sram 157then: 158 required: 159 - "#address-cells" 160 - "#size-cells" 161 - ranges 162 163additionalProperties: false 164 165examples: 166 - | 167 sram@5c000000 { 168 compatible = "mmio-sram"; 169 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 170 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges = <0 0x5c000000 0x40000>; 174 175 smp-sram@100 { 176 reg = <0x100 0x50>; 177 }; 178 179 device-sram@1000 { 180 reg = <0x1000 0x1000>; 181 pool; 182 }; 183 184 exported-sram@20000 { 185 reg = <0x20000 0x20000>; 186 export; 187 }; 188 }; 189 190 - | 191 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 192 // of the secondary cores. Once the core gets powered up it executes the 193 // code that is residing at some specific location of the SYSRAM. 194 // 195 // Therefore reserved section sub-nodes have to be added to the mmio-sram 196 // declaration. These nodes are of two types depending upon secure or 197 // non-secure execution environment. 198 sram@2020000 { 199 compatible = "mmio-sram"; 200 reg = <0x02020000 0x54000>; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges = <0 0x02020000 0x54000>; 204 205 smp-sram@0 { 206 compatible = "samsung,exynos4210-sysram"; 207 reg = <0x0 0x1000>; 208 }; 209 210 smp-sram@53000 { 211 compatible = "samsung,exynos4210-sysram-ns"; 212 reg = <0x53000 0x1000>; 213 }; 214 }; 215 216 - | 217 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 218 // Once the core gets powered up it executes the code that is residing at a 219 // specific location. 220 // 221 // Therefore a reserved section sub-node has to be added to the mmio-sram 222 // declaration. 223 sram@d9000000 { 224 compatible = "mmio-sram"; 225 reg = <0xd9000000 0x20000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0 0xd9000000 0x20000>; 229 230 smp-sram@1ff80 { 231 compatible = "amlogic,meson8b-smp-sram"; 232 reg = <0x1ff80 0x8>; 233 }; 234 }; 235 236 - | 237 sram@e63c0000 { 238 compatible = "mmio-sram"; 239 reg = <0xe63c0000 0x1000>; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 ranges = <0 0xe63c0000 0x1000>; 243 244 smp-sram@0 { 245 compatible = "renesas,smp-sram"; 246 reg = <0 0x10>; 247 }; 248 }; 249 250 - | 251 sram@10080000 { 252 compatible = "mmio-sram"; 253 reg = <0x10080000 0x10000>; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 ranges; 257 258 smp-sram@10080000 { 259 compatible = "rockchip,rk3066-smp-sram"; 260 reg = <0x10080000 0x50>; 261 }; 262 }; 263 264 - | 265 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 266 // resume from maskrom(the 1st level loader). This is a common use of 267 // the "pmu-sram" because it keeps power even in low power states 268 // in the system. 269 sram@ff720000 { 270 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 271 reg = <0xff720000 0x1000>; 272 }; 273 274 - | 275 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 276 // primary core (cpu0). Once the core gets powered up it checks if a magic 277 // value is set at a specific location. If it is then the BROM will jump 278 // to the software entry address, instead of executing a standard boot. 279 // 280 // Also there are no "secure-only" properties. The implementation should 281 // check if this SRAM is usable first. 282 sram@20000 { 283 // 256 KiB secure SRAM at 0x20000 284 compatible = "mmio-sram"; 285 reg = <0x00020000 0x40000>; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges = <0 0x00020000 0x40000>; 289 290 smp-sram@1000 { 291 // This is checked by BROM to determine if 292 // cpu0 should jump to SMP entry vector 293 compatible = "allwinner,sun9i-a80-smp-sram"; 294 reg = <0x1000 0x8>; 295 }; 296 }; 297 298 - | 299 sram@0 { 300 compatible = "mmio-sram"; 301 reg = <0x0 0x10000>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges = <0 0x0 0x10000>; 305 306 smp-sram@f100 { 307 compatible = "socionext,milbeaut-smp-sram"; 308 reg = <0xf100 0x20>; 309 }; 310 }; 311