1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,eliza-imem 38 - qcom,glymur-imem 39 - qcom,hawi-imem 40 - qcom,kaanapali-imem 41 - qcom,maili-imem 42 - qcom,milos-imem 43 - qcom,rpm-msg-ram 44 - qcom,shikra-imem 45 - rockchip,rk3288-pmu-sram 46 47 reg: 48 maxItems: 1 49 50 clocks: 51 maxItems: 1 52 description: 53 A list of phandle and clock specifier pair that controls the single 54 SRAM clock. 55 56 "#address-cells": 57 const: 1 58 59 "#size-cells": 60 const: 1 61 62 ranges: 63 maxItems: 1 64 description: 65 Should translate from local addresses within the sram to bus addresses. 66 67 no-memory-wc: 68 description: 69 The flag indicating, that SRAM memory region has not to be remapped 70 as write combining. WC is used by default. 71 type: boolean 72 73patternProperties: 74 "^([a-z0-9]+-)*sram(-section)?@[a-f0-9]+$": 75 type: object 76 description: 77 Each child of the sram node specifies a region of reserved memory. 78 properties: 79 compatible: 80 description: 81 Should contain a vendor specific string in the form 82 <vendor>,[<device>-]<usage> 83 contains: 84 enum: 85 - allwinner,sun4i-a10-sram-a3-a4 86 - allwinner,sun4i-a10-sram-c1 87 - allwinner,sun4i-a10-sram-d 88 - allwinner,sun9i-a80-smp-sram 89 - allwinner,sun50i-a64-sram-c 90 - allwinner,sun50i-h616-ve-sram 91 - amlogic,meson8-ao-arc-sram 92 - amlogic,meson8b-ao-arc-sram 93 - amlogic,meson8-smp-sram 94 - amlogic,meson8b-smp-sram 95 - amlogic,meson-gxbb-scp-shmem 96 - amlogic,meson-axg-scp-shmem 97 - arm,juno-scp-shmem 98 - arm,scmi-shmem 99 - arm,scp-shmem 100 - qcom,pil-reloc-info 101 - renesas,smp-sram 102 - rockchip,rk3066-smp-sram 103 - samsung,exynos4210-sysram 104 - samsung,exynos4210-sysram-ns 105 - socionext,milbeaut-smp-sram 106 - stericsson,u8500-esram 107 108 reg: 109 description: 110 IO mem address range, relative to the SRAM range. 111 maxItems: 1 112 113 reg-io-width: 114 description: 115 The size (in bytes) of the IO accesses that should be performed on the 116 SRAM. 117 enum: [1, 2, 4, 8] 118 119 pool: 120 description: 121 Indicates that the particular reserved SRAM area is addressable 122 and in use by another device or devices. 123 type: boolean 124 125 export: 126 description: 127 Indicates that the reserved SRAM area may be accessed outside 128 of the kernel, e.g. by bootloader or userspace. 129 type: boolean 130 131 protect-exec: 132 description: | 133 Same as 'pool' above but with the additional constraint that code 134 will be run from the region and that the memory is maintained as 135 read-only, executable during code execution. NOTE: This region must 136 be page aligned on start and end in order to properly allow 137 manipulation of the page attributes. 138 type: boolean 139 140 label: 141 description: 142 The name for the reserved partition, if omitted, the label is taken 143 from the node name excluding the unit address. 144 145 required: 146 - reg 147 148 additionalProperties: false 149 150required: 151 - compatible 152 - reg 153 154if: 155 not: 156 properties: 157 compatible: 158 contains: 159 enum: 160 - qcom,rpm-msg-ram 161 - rockchip,rk3288-pmu-sram 162then: 163 required: 164 - "#address-cells" 165 - "#size-cells" 166 - ranges 167 168additionalProperties: false 169 170examples: 171 - | 172 sram@5c000000 { 173 compatible = "mmio-sram"; 174 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 175 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges = <0 0x5c000000 0x40000>; 179 180 smp-sram@100 { 181 reg = <0x100 0x50>; 182 }; 183 184 device-sram@1000 { 185 reg = <0x1000 0x1000>; 186 pool; 187 }; 188 189 exported-sram@20000 { 190 reg = <0x20000 0x20000>; 191 export; 192 }; 193 }; 194 195 - | 196 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 197 // of the secondary cores. Once the core gets powered up it executes the 198 // code that is residing at some specific location of the SYSRAM. 199 // 200 // Therefore reserved section sub-nodes have to be added to the mmio-sram 201 // declaration. These nodes are of two types depending upon secure or 202 // non-secure execution environment. 203 sram@2020000 { 204 compatible = "mmio-sram"; 205 reg = <0x02020000 0x54000>; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 ranges = <0 0x02020000 0x54000>; 209 210 smp-sram@0 { 211 compatible = "samsung,exynos4210-sysram"; 212 reg = <0x0 0x1000>; 213 }; 214 215 smp-sram@53000 { 216 compatible = "samsung,exynos4210-sysram-ns"; 217 reg = <0x53000 0x1000>; 218 }; 219 }; 220 221 - | 222 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 223 // Once the core gets powered up it executes the code that is residing at a 224 // specific location. 225 // 226 // Therefore a reserved section sub-node has to be added to the mmio-sram 227 // declaration. 228 sram@d9000000 { 229 compatible = "mmio-sram"; 230 reg = <0xd9000000 0x20000>; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 ranges = <0 0xd9000000 0x20000>; 234 235 smp-sram@1ff80 { 236 compatible = "amlogic,meson8b-smp-sram"; 237 reg = <0x1ff80 0x8>; 238 }; 239 }; 240 241 - | 242 sram@e63c0000 { 243 compatible = "mmio-sram"; 244 reg = <0xe63c0000 0x1000>; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 ranges = <0 0xe63c0000 0x1000>; 248 249 smp-sram@0 { 250 compatible = "renesas,smp-sram"; 251 reg = <0 0x10>; 252 }; 253 }; 254 255 - | 256 sram@10080000 { 257 compatible = "mmio-sram"; 258 reg = <0x10080000 0x10000>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 ranges; 262 263 smp-sram@10080000 { 264 compatible = "rockchip,rk3066-smp-sram"; 265 reg = <0x10080000 0x50>; 266 }; 267 }; 268 269 - | 270 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 271 // resume from maskrom(the 1st level loader). This is a common use of 272 // the "pmu-sram" because it keeps power even in low power states 273 // in the system. 274 sram@ff720000 { 275 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 276 reg = <0xff720000 0x1000>; 277 }; 278 279 - | 280 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 281 // primary core (cpu0). Once the core gets powered up it checks if a magic 282 // value is set at a specific location. If it is then the BROM will jump 283 // to the software entry address, instead of executing a standard boot. 284 // 285 // Also there are no "secure-only" properties. The implementation should 286 // check if this SRAM is usable first. 287 sram@20000 { 288 // 256 KiB secure SRAM at 0x20000 289 compatible = "mmio-sram"; 290 reg = <0x00020000 0x40000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges = <0 0x00020000 0x40000>; 294 295 smp-sram@1000 { 296 // This is checked by BROM to determine if 297 // cpu0 should jump to SMP entry vector 298 compatible = "allwinner,sun9i-a80-smp-sram"; 299 reg = <0x1000 0x8>; 300 }; 301 }; 302 303 - | 304 sram@0 { 305 compatible = "mmio-sram"; 306 reg = <0x0 0x10000>; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 ranges = <0 0x0 0x10000>; 310 311 smp-sram@f100 { 312 compatible = "socionext,milbeaut-smp-sram"; 313 reg = <0xf100 0x20>; 314 }; 315 }; 316