1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,eliza-imem 38 - qcom,glymur-imem 39 - qcom,hawi-imem 40 - qcom,ipq5424-imem 41 - qcom,kaanapali-imem 42 - qcom,maili-imem 43 - qcom,milos-imem 44 - qcom,rpm-msg-ram 45 - qcom,shikra-imem 46 - rockchip,rk3288-pmu-sram 47 - samsung,exynos850-acpm-sram 48 49 reg: 50 maxItems: 1 51 52 clocks: 53 maxItems: 1 54 description: 55 A list of phandle and clock specifier pair that controls the single 56 SRAM clock. 57 58 "#address-cells": 59 const: 1 60 61 "#size-cells": 62 const: 1 63 64 ranges: 65 maxItems: 1 66 description: 67 Should translate from local addresses within the sram to bus addresses. 68 69 no-memory-wc: 70 description: 71 The flag indicating, that SRAM memory region has not to be remapped 72 as write combining. WC is used by default. 73 type: boolean 74 75patternProperties: 76 "^([a-z0-9]+-)*sram(-section)?@[a-f0-9]+$": 77 type: object 78 description: 79 Each child of the sram node specifies a region of reserved memory. 80 properties: 81 compatible: 82 description: 83 Should contain a vendor specific string in the form 84 <vendor>,[<device>-]<usage> 85 contains: 86 enum: 87 - allwinner,sun4i-a10-sram-a3-a4 88 - allwinner,sun4i-a10-sram-c1 89 - allwinner,sun4i-a10-sram-d 90 - allwinner,sun9i-a80-smp-sram 91 - allwinner,sun50i-a64-sram-c 92 - allwinner,sun50i-h616-ve-sram 93 - amlogic,meson8-ao-arc-sram 94 - amlogic,meson8b-ao-arc-sram 95 - amlogic,meson8-smp-sram 96 - amlogic,meson8b-smp-sram 97 - amlogic,meson-gxbb-scp-shmem 98 - amlogic,meson-axg-scp-shmem 99 - arm,juno-scp-shmem 100 - arm,scmi-shmem 101 - arm,scp-shmem 102 - qcom,pil-reloc-info 103 - renesas,smp-sram 104 - rockchip,rk3066-smp-sram 105 - samsung,exynos4210-sysram 106 - samsung,exynos4210-sysram-ns 107 - socionext,milbeaut-smp-sram 108 - stericsson,u8500-esram 109 110 reg: 111 description: 112 IO mem address range, relative to the SRAM range. 113 maxItems: 1 114 115 reg-io-width: 116 description: 117 The size (in bytes) of the IO accesses that should be performed on the 118 SRAM. 119 enum: [1, 2, 4, 8] 120 121 pool: 122 description: 123 Indicates that the particular reserved SRAM area is addressable 124 and in use by another device or devices. 125 type: boolean 126 127 export: 128 description: 129 Indicates that the reserved SRAM area may be accessed outside 130 of the kernel, e.g. by bootloader or userspace. 131 type: boolean 132 133 protect-exec: 134 description: | 135 Same as 'pool' above but with the additional constraint that code 136 will be run from the region and that the memory is maintained as 137 read-only, executable during code execution. NOTE: This region must 138 be page aligned on start and end in order to properly allow 139 manipulation of the page attributes. 140 type: boolean 141 142 label: 143 description: 144 The name for the reserved partition, if omitted, the label is taken 145 from the node name excluding the unit address. 146 147 required: 148 - reg 149 150 additionalProperties: false 151 152required: 153 - compatible 154 - reg 155 156if: 157 not: 158 properties: 159 compatible: 160 contains: 161 enum: 162 - qcom,rpm-msg-ram 163 - rockchip,rk3288-pmu-sram 164 - samsung,exynos850-acpm-sram 165then: 166 required: 167 - "#address-cells" 168 - "#size-cells" 169 - ranges 170 171additionalProperties: false 172 173examples: 174 - | 175 sram@5c000000 { 176 compatible = "mmio-sram"; 177 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 178 179 #address-cells = <1>; 180 #size-cells = <1>; 181 ranges = <0 0x5c000000 0x40000>; 182 183 smp-sram@100 { 184 reg = <0x100 0x50>; 185 }; 186 187 device-sram@1000 { 188 reg = <0x1000 0x1000>; 189 pool; 190 }; 191 192 exported-sram@20000 { 193 reg = <0x20000 0x20000>; 194 export; 195 }; 196 }; 197 198 - | 199 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 200 // of the secondary cores. Once the core gets powered up it executes the 201 // code that is residing at some specific location of the SYSRAM. 202 // 203 // Therefore reserved section sub-nodes have to be added to the mmio-sram 204 // declaration. These nodes are of two types depending upon secure or 205 // non-secure execution environment. 206 sram@2020000 { 207 compatible = "mmio-sram"; 208 reg = <0x02020000 0x54000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0 0x02020000 0x54000>; 212 213 smp-sram@0 { 214 compatible = "samsung,exynos4210-sysram"; 215 reg = <0x0 0x1000>; 216 }; 217 218 smp-sram@53000 { 219 compatible = "samsung,exynos4210-sysram-ns"; 220 reg = <0x53000 0x1000>; 221 }; 222 }; 223 224 - | 225 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 226 // Once the core gets powered up it executes the code that is residing at a 227 // specific location. 228 // 229 // Therefore a reserved section sub-node has to be added to the mmio-sram 230 // declaration. 231 sram@d9000000 { 232 compatible = "mmio-sram"; 233 reg = <0xd9000000 0x20000>; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 ranges = <0 0xd9000000 0x20000>; 237 238 smp-sram@1ff80 { 239 compatible = "amlogic,meson8b-smp-sram"; 240 reg = <0x1ff80 0x8>; 241 }; 242 }; 243 244 - | 245 sram@e63c0000 { 246 compatible = "mmio-sram"; 247 reg = <0xe63c0000 0x1000>; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges = <0 0xe63c0000 0x1000>; 251 252 smp-sram@0 { 253 compatible = "renesas,smp-sram"; 254 reg = <0 0x10>; 255 }; 256 }; 257 258 - | 259 sram@10080000 { 260 compatible = "mmio-sram"; 261 reg = <0x10080000 0x10000>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges; 265 266 smp-sram@10080000 { 267 compatible = "rockchip,rk3066-smp-sram"; 268 reg = <0x10080000 0x50>; 269 }; 270 }; 271 272 - | 273 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 274 // resume from maskrom(the 1st level loader). This is a common use of 275 // the "pmu-sram" because it keeps power even in low power states 276 // in the system. 277 sram@ff720000 { 278 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 279 reg = <0xff720000 0x1000>; 280 }; 281 282 - | 283 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 284 // primary core (cpu0). Once the core gets powered up it checks if a magic 285 // value is set at a specific location. If it is then the BROM will jump 286 // to the software entry address, instead of executing a standard boot. 287 // 288 // Also there are no "secure-only" properties. The implementation should 289 // check if this SRAM is usable first. 290 sram@20000 { 291 // 256 KiB secure SRAM at 0x20000 292 compatible = "mmio-sram"; 293 reg = <0x00020000 0x40000>; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 ranges = <0 0x00020000 0x40000>; 297 298 smp-sram@1000 { 299 // This is checked by BROM to determine if 300 // cpu0 should jump to SMP entry vector 301 compatible = "allwinner,sun9i-a80-smp-sram"; 302 reg = <0x1000 0x8>; 303 }; 304 }; 305 306 - | 307 sram@0 { 308 compatible = "mmio-sram"; 309 reg = <0x0 0x10000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges = <0 0x0 0x10000>; 313 314 smp-sram@f100 { 315 compatible = "socionext,milbeaut-smp-sram"; 316 reg = <0xf100 0x20>; 317 }; 318 }; 319