1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sram/sram.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic on-chip SRAM 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 Simple IO memory regions to be managed by the genalloc API. 14 15 Each child of the sram node specifies a region of reserved memory. Each 16 child node should use a 'reg' property to specify a specific range of 17 reserved memory. 18 19 Following the generic-names recommended practice, node names should 20 reflect the purpose of the node. Unit address (@<address>) should be 21 appended to the name. 22 23properties: 24 $nodename: 25 pattern: "^sram(@.*)?" 26 27 compatible: 28 contains: 29 enum: 30 - mmio-sram 31 - amlogic,meson-gxbb-sram 32 - arm,juno-sram-ns 33 - atmel,sama5d2-securam 34 - nvidia,tegra186-sysram 35 - nvidia,tegra194-sysram 36 - nvidia,tegra234-sysram 37 - qcom,rpm-msg-ram 38 - rockchip,rk3288-pmu-sram 39 40 reg: 41 maxItems: 1 42 43 clocks: 44 maxItems: 1 45 description: 46 A list of phandle and clock specifier pair that controls the single 47 SRAM clock. 48 49 "#address-cells": 50 const: 1 51 52 "#size-cells": 53 const: 1 54 55 ranges: 56 maxItems: 1 57 description: 58 Should translate from local addresses within the sram to bus addresses. 59 60 no-memory-wc: 61 description: 62 The flag indicating, that SRAM memory region has not to be remapped 63 as write combining. WC is used by default. 64 type: boolean 65 66patternProperties: 67 "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$": 68 type: object 69 description: 70 Each child of the sram node specifies a region of reserved memory. 71 properties: 72 compatible: 73 description: 74 Should contain a vendor specific string in the form 75 <vendor>,[<device>-]<usage> 76 contains: 77 enum: 78 - allwinner,sun4i-a10-sram-a3-a4 79 - allwinner,sun4i-a10-sram-c1 80 - allwinner,sun4i-a10-sram-d 81 - allwinner,sun9i-a80-smp-sram 82 - allwinner,sun50i-a64-sram-c 83 - amlogic,meson8-ao-arc-sram 84 - amlogic,meson8b-ao-arc-sram 85 - amlogic,meson8-smp-sram 86 - amlogic,meson8b-smp-sram 87 - amlogic,meson-gxbb-scp-shmem 88 - amlogic,meson-axg-scp-shmem 89 - arm,juno-scp-shmem 90 - arm,scmi-shmem 91 - arm,scp-shmem 92 - renesas,smp-sram 93 - rockchip,rk3066-smp-sram 94 - samsung,exynos4210-sysram 95 - samsung,exynos4210-sysram-ns 96 - socionext,milbeaut-smp-sram 97 98 reg: 99 description: 100 IO mem address range, relative to the SRAM range. 101 maxItems: 1 102 103 pool: 104 description: 105 Indicates that the particular reserved SRAM area is addressable 106 and in use by another device or devices. 107 type: boolean 108 109 export: 110 description: 111 Indicates that the reserved SRAM area may be accessed outside 112 of the kernel, e.g. by bootloader or userspace. 113 type: boolean 114 115 protect-exec: 116 description: | 117 Same as 'pool' above but with the additional constraint that code 118 will be run from the region and that the memory is maintained as 119 read-only, executable during code execution. NOTE: This region must 120 be page aligned on start and end in order to properly allow 121 manipulation of the page attributes. 122 type: boolean 123 124 label: 125 description: 126 The name for the reserved partition, if omitted, the label is taken 127 from the node name excluding the unit address. 128 129 required: 130 - reg 131 132 additionalProperties: false 133 134required: 135 - compatible 136 - reg 137 138if: 139 not: 140 properties: 141 compatible: 142 contains: 143 enum: 144 - qcom,rpm-msg-ram 145 - rockchip,rk3288-pmu-sram 146then: 147 required: 148 - "#address-cells" 149 - "#size-cells" 150 - ranges 151 152additionalProperties: false 153 154examples: 155 - | 156 sram@5c000000 { 157 compatible = "mmio-sram"; 158 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ 159 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges = <0 0x5c000000 0x40000>; 163 164 smp-sram@100 { 165 reg = <0x100 0x50>; 166 }; 167 168 device-sram@1000 { 169 reg = <0x1000 0x1000>; 170 pool; 171 }; 172 173 exported-sram@20000 { 174 reg = <0x20000 0x20000>; 175 export; 176 }; 177 }; 178 179 - | 180 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup 181 // of the secondary cores. Once the core gets powered up it executes the 182 // code that is residing at some specific location of the SYSRAM. 183 // 184 // Therefore reserved section sub-nodes have to be added to the mmio-sram 185 // declaration. These nodes are of two types depending upon secure or 186 // non-secure execution environment. 187 sram@2020000 { 188 compatible = "mmio-sram"; 189 reg = <0x02020000 0x54000>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 ranges = <0 0x02020000 0x54000>; 193 194 smp-sram@0 { 195 compatible = "samsung,exynos4210-sysram"; 196 reg = <0x0 0x1000>; 197 }; 198 199 smp-sram@53000 { 200 compatible = "samsung,exynos4210-sysram-ns"; 201 reg = <0x53000 0x1000>; 202 }; 203 }; 204 205 - | 206 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. 207 // Once the core gets powered up it executes the code that is residing at a 208 // specific location. 209 // 210 // Therefore a reserved section sub-node has to be added to the mmio-sram 211 // declaration. 212 sram@d9000000 { 213 compatible = "mmio-sram"; 214 reg = <0xd9000000 0x20000>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges = <0 0xd9000000 0x20000>; 218 219 smp-sram@1ff80 { 220 compatible = "amlogic,meson8b-smp-sram"; 221 reg = <0x1ff80 0x8>; 222 }; 223 }; 224 225 - | 226 sram@e63c0000 { 227 compatible = "mmio-sram"; 228 reg = <0xe63c0000 0x1000>; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 ranges = <0 0xe63c0000 0x1000>; 232 233 smp-sram@0 { 234 compatible = "renesas,smp-sram"; 235 reg = <0 0x10>; 236 }; 237 }; 238 239 - | 240 sram@10080000 { 241 compatible = "mmio-sram"; 242 reg = <0x10080000 0x10000>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 ranges; 246 247 smp-sram@10080000 { 248 compatible = "rockchip,rk3066-smp-sram"; 249 reg = <0x10080000 0x50>; 250 }; 251 }; 252 253 - | 254 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of 255 // resume from maskrom(the 1st level loader). This is a common use of 256 // the "pmu-sram" because it keeps power even in low power states 257 // in the system. 258 sram@ff720000 { 259 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 260 reg = <0xff720000 0x1000>; 261 }; 262 263 - | 264 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the 265 // primary core (cpu0). Once the core gets powered up it checks if a magic 266 // value is set at a specific location. If it is then the BROM will jump 267 // to the software entry address, instead of executing a standard boot. 268 // 269 // Also there are no "secure-only" properties. The implementation should 270 // check if this SRAM is usable first. 271 sram@20000 { 272 // 256 KiB secure SRAM at 0x20000 273 compatible = "mmio-sram"; 274 reg = <0x00020000 0x40000>; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges = <0 0x00020000 0x40000>; 278 279 smp-sram@1000 { 280 // This is checked by BROM to determine if 281 // cpu0 should jump to SMP entry vector 282 compatible = "allwinner,sun9i-a80-smp-sram"; 283 reg = <0x1000 0x8>; 284 }; 285 }; 286 287 - | 288 sram@0 { 289 compatible = "mmio-sram"; 290 reg = <0x0 0x10000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges = <0 0x0 0x10000>; 294 295 smp-sram@f100 { 296 compatible = "socionext,milbeaut-smp-sram"; 297 reg = <0xf100 0x20>; 298 }; 299 }; 300