1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STMicroelectronics STM32 SPI Controller 8 9description: | 10 The STM32 SPI controller is used to communicate with external devices using 11 the Serial Peripheral Interface. It supports full-duplex, half-duplex and 12 simplex synchronous serial communication with external devices. It supports 13 from 4 to 32-bit data size. 14 15maintainers: 16 - Erwan Leray <erwan.leray@foss.st.com> 17 - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 18 19allOf: 20 - $ref: spi-controller.yaml# 21 - if: 22 properties: 23 compatible: 24 contains: 25 const: st,stm32f4-spi 26 27 then: 28 properties: 29 st,spi-midi-ns: false 30 sram: false 31 dmas: 32 maxItems: 2 33 dma-names: 34 items: 35 - const: rx 36 - const: tx 37 38 - if: 39 properties: 40 compatible: 41 contains: 42 const: st,stm32mp25-spi 43 44 then: 45 properties: 46 sram: false 47 dmas: 48 maxItems: 2 49 dma-names: 50 items: 51 - const: rx 52 - const: tx 53 54properties: 55 compatible: 56 enum: 57 - st,stm32f4-spi 58 - st,stm32f7-spi 59 - st,stm32h7-spi 60 - st,stm32mp25-spi 61 62 reg: 63 maxItems: 1 64 65 clocks: 66 maxItems: 1 67 68 interrupts: 69 maxItems: 1 70 71 resets: 72 maxItems: 1 73 74 dmas: 75 description: | 76 DMA specifiers for tx and rx channels. DMA fifo mode must be used. See 77 the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32/st,*dma.yaml 78 minItems: 2 79 items: 80 - description: rx DMA channel 81 - description: tx DMA channel 82 - description: rxm2m MDMA channel 83 84 dma-names: 85 minItems: 2 86 items: 87 - const: rx 88 - const: tx 89 - const: rxm2m 90 91 sram: 92 $ref: /schemas/types.yaml#/definitions/phandle 93 description: | 94 Phandles to a reserved SRAM region which is used as temporary 95 storage memory between DMA and MDMA engines. 96 The region should be defined as child node of the AHB SRAM node 97 as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml 98 99 access-controllers: 100 minItems: 1 101 maxItems: 2 102 103required: 104 - compatible 105 - reg 106 - clocks 107 - interrupts 108 109unevaluatedProperties: false 110 111examples: 112 - | 113 #include <dt-bindings/interrupt-controller/arm-gic.h> 114 #include <dt-bindings/clock/stm32mp1-clks.h> 115 #include <dt-bindings/reset/stm32mp1-resets.h> 116 spi@4000b000 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 compatible = "st,stm32h7-spi"; 120 reg = <0x4000b000 0x400>; 121 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&rcc SPI2_K>; 123 resets = <&rcc SPI2_R>; 124 dmas = <&dmamux1 0 39 0x400 0x05>, 125 <&dmamux1 1 40 0x400 0x05>; 126 dma-names = "rx", "tx"; 127 cs-gpios = <&gpioa 11 0>; 128 }; 129 130... 131