xref: /linux/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1ef32b63bSBenjamin Gaignard# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2ef32b63bSBenjamin Gaignard%YAML 1.2
3ef32b63bSBenjamin Gaignard---
4ef32b63bSBenjamin Gaignard$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
5ef32b63bSBenjamin Gaignard$schema: http://devicetree.org/meta-schemas/core.yaml#
6ef32b63bSBenjamin Gaignard
784e85359SKrzysztof Kozlowskititle: STMicroelectronics STM32 SPI Controller
8ef32b63bSBenjamin Gaignard
9ef32b63bSBenjamin Gaignarddescription: |
10ef32b63bSBenjamin Gaignard  The STM32 SPI controller is used to communicate with external devices using
11ef32b63bSBenjamin Gaignard  the Serial Peripheral Interface. It supports full-duplex, half-duplex and
12ef32b63bSBenjamin Gaignard  simplex synchronous serial communication with external devices. It supports
13ef32b63bSBenjamin Gaignard  from 4 to 32-bit data size.
14ef32b63bSBenjamin Gaignard
15ef32b63bSBenjamin Gaignardmaintainers:
16f4eedebdSPatrice Chotard  - Erwan Leray <erwan.leray@foss.st.com>
17f4eedebdSPatrice Chotard  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
18ef32b63bSBenjamin Gaignard
19ef32b63bSBenjamin GaignardallOf:
2099a7fa0eSKrzysztof Kozlowski  - $ref: spi-controller.yaml#
21ef32b63bSBenjamin Gaignard
22ef32b63bSBenjamin Gaignardproperties:
23ef32b63bSBenjamin Gaignard  compatible:
24ef32b63bSBenjamin Gaignard    enum:
25ef32b63bSBenjamin Gaignard      - st,stm32f4-spi
2609388379SBen Wolsieffer      - st,stm32f7-spi
27ef32b63bSBenjamin Gaignard      - st,stm32h7-spi
28f034a151SValentin Caron      - st,stm32mp25-spi
29ef32b63bSBenjamin Gaignard
30ef32b63bSBenjamin Gaignard  reg:
31ef32b63bSBenjamin Gaignard    maxItems: 1
32ef32b63bSBenjamin Gaignard
33ef32b63bSBenjamin Gaignard  clocks:
34ef32b63bSBenjamin Gaignard    maxItems: 1
35ef32b63bSBenjamin Gaignard
36ef32b63bSBenjamin Gaignard  interrupts:
37ef32b63bSBenjamin Gaignard    maxItems: 1
38ef32b63bSBenjamin Gaignard
39ef32b63bSBenjamin Gaignard  resets:
40ef32b63bSBenjamin Gaignard    maxItems: 1
41ef32b63bSBenjamin Gaignard
42ef32b63bSBenjamin Gaignard  dmas:
43ef32b63bSBenjamin Gaignard    description: |
44ef32b63bSBenjamin Gaignard      DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
45*8494ae75SAmelie Delaunay      the STM32 DMA controllers bindings Documentation/devicetree/bindings/dma/stm32/*.yaml.
46ef32b63bSBenjamin Gaignard    items:
47ef32b63bSBenjamin Gaignard      - description: rx DMA channel
48ef32b63bSBenjamin Gaignard      - description: tx DMA channel
49ef32b63bSBenjamin Gaignard
50ef32b63bSBenjamin Gaignard  dma-names:
51ef32b63bSBenjamin Gaignard    items:
52ef32b63bSBenjamin Gaignard      - const: rx
53ef32b63bSBenjamin Gaignard      - const: tx
54ef32b63bSBenjamin Gaignard
5502ec75edSGatien Chevallier  access-controllers:
5602ec75edSGatien Chevallier    minItems: 1
5702ec75edSGatien Chevallier    maxItems: 2
5802ec75edSGatien Chevallier
59ef32b63bSBenjamin Gaignardrequired:
60ef32b63bSBenjamin Gaignard  - compatible
61ef32b63bSBenjamin Gaignard  - reg
62ef32b63bSBenjamin Gaignard  - clocks
63ef32b63bSBenjamin Gaignard  - interrupts
64ef32b63bSBenjamin Gaignard
656fdc6e23SRob HerringunevaluatedProperties: false
666fdc6e23SRob Herring
67ef32b63bSBenjamin Gaignardexamples:
68ef32b63bSBenjamin Gaignard  - |
69ef32b63bSBenjamin Gaignard    #include <dt-bindings/interrupt-controller/arm-gic.h>
70ef32b63bSBenjamin Gaignard    #include <dt-bindings/clock/stm32mp1-clks.h>
71ef32b63bSBenjamin Gaignard    #include <dt-bindings/reset/stm32mp1-resets.h>
72ef32b63bSBenjamin Gaignard    spi@4000b000 {
73ef32b63bSBenjamin Gaignard        #address-cells = <1>;
74ef32b63bSBenjamin Gaignard        #size-cells = <0>;
75ef32b63bSBenjamin Gaignard        compatible = "st,stm32h7-spi";
76ef32b63bSBenjamin Gaignard        reg = <0x4000b000 0x400>;
77ef32b63bSBenjamin Gaignard        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
78ef32b63bSBenjamin Gaignard        clocks = <&rcc SPI2_K>;
79ef32b63bSBenjamin Gaignard        resets = <&rcc SPI2_R>;
80ef32b63bSBenjamin Gaignard        dmas = <&dmamux1 0 39 0x400 0x05>,
81ef32b63bSBenjamin Gaignard               <&dmamux1 1 40 0x400 0x05>;
82ef32b63bSBenjamin Gaignard        dma-names = "rx", "tx";
83ef32b63bSBenjamin Gaignard        cs-gpios = <&gpioa 11 0>;
84ef32b63bSBenjamin Gaignard    };
85ef32b63bSBenjamin Gaignard
86ef32b63bSBenjamin Gaignard...
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