xref: /linux/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml (revision da1d9caf95def6f0320819cf941c9fd1069ba9e1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
8
9maintainers:
10  - Michal Simek <michal.simek@xilinx.com>
11
12allOf:
13  - $ref: "spi-controller.yaml#"
14
15properties:
16  compatible:
17    const: xlnx,zynqmp-qspi-1.0
18
19  reg:
20    maxItems: 2
21
22  interrupts:
23    maxItems: 1
24
25  clock-names:
26    items:
27      - const: ref_clk
28      - const: pclk
29
30  clocks:
31    maxItems: 2
32
33unevaluatedProperties: false
34
35examples:
36  - |
37    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
38    soc {
39      #address-cells = <2>;
40      #size-cells = <2>;
41
42      qspi: spi@ff0f0000 {
43        compatible = "xlnx,zynqmp-qspi-1.0";
44        clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
45        clock-names = "ref_clk", "pclk";
46        interrupts = <0 15 4>;
47        interrupt-parent = <&gic>;
48        reg = <0x0 0xff0f0000 0x0 0x1000>,
49              <0x0 0xc0000000 0x0 0x8000000>;
50      };
51    };
52