xref: /linux/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
8
9maintainers:
10  - Michal Simek <michal.simek@amd.com>
11
12properties:
13  compatible:
14    enum:
15      - xlnx,versal-qspi-1.0
16      - xlnx,zynqmp-qspi-1.0
17
18  reg:
19    minItems: 1
20    maxItems: 2
21
22  interrupts:
23    maxItems: 1
24
25  clock-names:
26    items:
27      - const: ref_clk
28      - const: pclk
29
30  clocks:
31    maxItems: 2
32
33  iommus:
34    maxItems: 1
35
36  power-domains:
37    maxItems: 1
38
39required:
40  - compatible
41  - reg
42  - interrupts
43  - clock-names
44  - clocks
45
46unevaluatedProperties: false
47
48allOf:
49  - $ref: spi-controller.yaml#
50
51  - if:
52      properties:
53        compatible:
54          contains:
55            const: xlnx,zynqmp-qspi-1.0
56    then:
57      properties:
58        reg:
59          minItems: 2
60
61    else:
62      properties:
63        reg:
64          maxItems: 1
65
66examples:
67  - |
68    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
69    soc {
70      #address-cells = <2>;
71      #size-cells = <2>;
72
73      qspi: spi@ff0f0000 {
74        compatible = "xlnx,zynqmp-qspi-1.0";
75        clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
76        clock-names = "ref_clk", "pclk";
77        interrupts = <0 15 4>;
78        interrupt-parent = <&gic>;
79        reg = <0x0 0xff0f0000 0x0 0x1000>,
80              <0x0 0xc0000000 0x0 0x8000000>;
81      };
82    };
83