xref: /linux/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml (revision 5e64ee4204479ed2bf2abd7d6095686288ea008f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
8
9maintainers:
10  - Michal Simek <michal.simek@amd.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - xlnx,versal-qspi-1.0
19      - xlnx,zynqmp-qspi-1.0
20
21  reg:
22    maxItems: 2
23
24  interrupts:
25    maxItems: 1
26
27  clock-names:
28    items:
29      - const: ref_clk
30      - const: pclk
31
32  clocks:
33    maxItems: 2
34
35required:
36  - compatible
37  - reg
38  - interrupts
39  - clock-names
40  - clocks
41
42unevaluatedProperties: false
43
44examples:
45  - |
46    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
47    soc {
48      #address-cells = <2>;
49      #size-cells = <2>;
50
51      qspi: spi@ff0f0000 {
52        compatible = "xlnx,zynqmp-qspi-1.0";
53        clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
54        clock-names = "ref_clk", "pclk";
55        interrupts = <0 15 4>;
56        interrupt-parent = <&gic>;
57        reg = <0x0 0xff0f0000 0x0 0x1000>,
58              <0x0 0xc0000000 0x0 0x8000000>;
59      };
60    };
61