xref: /linux/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml (revision 0791faebfe750292a8a842b64795a390ca4a3b51) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
8
9maintainers:
10  - Michal Simek <michal.simek@amd.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - xlnx,versal-qspi-1.0
19      - xlnx,zynqmp-qspi-1.0
20
21  reg:
22    maxItems: 2
23
24  interrupts:
25    maxItems: 1
26
27  clock-names:
28    items:
29      - const: ref_clk
30      - const: pclk
31
32  clocks:
33    maxItems: 2
34
35  iommus:
36    maxItems: 1
37
38  power-domains:
39    maxItems: 1
40
41required:
42  - compatible
43  - reg
44  - interrupts
45  - clock-names
46  - clocks
47
48unevaluatedProperties: false
49
50examples:
51  - |
52    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
53    soc {
54      #address-cells = <2>;
55      #size-cells = <2>;
56
57      qspi: spi@ff0f0000 {
58        compatible = "xlnx,zynqmp-qspi-1.0";
59        clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
60        clock-names = "ref_clk", "pclk";
61        interrupts = <0 15 4>;
62        interrupt-parent = <&gic>;
63        reg = <0x0 0xff0f0000 0x0 0x1000>,
64              <0x0 0xc0000000 0x0 0x8000000>;
65      };
66    };
67