1*c58db2abSNobuhiro Iwamatsu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c58db2abSNobuhiro Iwamatsu%YAML 1.2 3*c58db2abSNobuhiro Iwamatsu--- 4*c58db2abSNobuhiro Iwamatsu$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml# 5*c58db2abSNobuhiro Iwamatsu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c58db2abSNobuhiro Iwamatsu 7*c58db2abSNobuhiro Iwamatsutitle: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings 8*c58db2abSNobuhiro Iwamatsu 9*c58db2abSNobuhiro Iwamatsumaintainers: 10*c58db2abSNobuhiro Iwamatsu - Michal Simek <michal.simek@xilinx.com> 11*c58db2abSNobuhiro Iwamatsu 12*c58db2abSNobuhiro IwamatsuallOf: 13*c58db2abSNobuhiro Iwamatsu - $ref: "spi-controller.yaml#" 14*c58db2abSNobuhiro Iwamatsu 15*c58db2abSNobuhiro Iwamatsuproperties: 16*c58db2abSNobuhiro Iwamatsu compatible: 17*c58db2abSNobuhiro Iwamatsu const: xlnx,zynqmp-qspi-1.0 18*c58db2abSNobuhiro Iwamatsu 19*c58db2abSNobuhiro Iwamatsu reg: 20*c58db2abSNobuhiro Iwamatsu maxItems: 2 21*c58db2abSNobuhiro Iwamatsu 22*c58db2abSNobuhiro Iwamatsu interrupts: 23*c58db2abSNobuhiro Iwamatsu maxItems: 1 24*c58db2abSNobuhiro Iwamatsu 25*c58db2abSNobuhiro Iwamatsu clock-names: 26*c58db2abSNobuhiro Iwamatsu items: 27*c58db2abSNobuhiro Iwamatsu - const: ref_clk 28*c58db2abSNobuhiro Iwamatsu - const: pclk 29*c58db2abSNobuhiro Iwamatsu 30*c58db2abSNobuhiro Iwamatsu clocks: 31*c58db2abSNobuhiro Iwamatsu maxItems: 2 32*c58db2abSNobuhiro Iwamatsu 33*c58db2abSNobuhiro IwamatsuunevaluatedProperties: false 34*c58db2abSNobuhiro Iwamatsu 35*c58db2abSNobuhiro Iwamatsuexamples: 36*c58db2abSNobuhiro Iwamatsu - | 37*c58db2abSNobuhiro Iwamatsu #include <dt-bindings/clock/xlnx-zynqmp-clk.h> 38*c58db2abSNobuhiro Iwamatsu soc { 39*c58db2abSNobuhiro Iwamatsu #address-cells = <2>; 40*c58db2abSNobuhiro Iwamatsu #size-cells = <2>; 41*c58db2abSNobuhiro Iwamatsu 42*c58db2abSNobuhiro Iwamatsu qspi: spi@ff0f0000 { 43*c58db2abSNobuhiro Iwamatsu compatible = "xlnx,zynqmp-qspi-1.0"; 44*c58db2abSNobuhiro Iwamatsu clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; 45*c58db2abSNobuhiro Iwamatsu clock-names = "ref_clk", "pclk"; 46*c58db2abSNobuhiro Iwamatsu interrupts = <0 15 4>; 47*c58db2abSNobuhiro Iwamatsu interrupt-parent = <&gic>; 48*c58db2abSNobuhiro Iwamatsu reg = <0x0 0xff0f0000 0x0 0x1000>, 49*c58db2abSNobuhiro Iwamatsu <0x0 0xc0000000 0x0 0x8000000>; 50*c58db2abSNobuhiro Iwamatsu }; 51*c58db2abSNobuhiro Iwamatsu }; 52