xref: /linux/Documentation/devicetree/bindings/spi/spi-sifive.yaml (revision 95298d63c67673c654c08952672d016212b26054) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive SPI controller
8
9maintainers:
10  - Pragnesh Patel <pragnesh.patel@sifive.com>
11  - Paul Walmsley  <paul.walmsley@sifive.com>
12  - Palmer Dabbelt <palmer@sifive.com>
13
14allOf:
15  - $ref: "spi-controller.yaml#"
16
17properties:
18  compatible:
19    items:
20      - const: sifive,fu540-c000-spi
21      - const: sifive,spi0
22
23    description:
24      Should be "sifive,<chip>-spi" and "sifive,spi<version>".
25      Supported compatible strings are -
26      "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
27      onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
28      SPI v0 IP block with no chip integration tweaks.
29      Please refer to sifive-blocks-ip-versioning.txt for details
30
31      SPI RTL that corresponds to the IP block version numbers can be found here -
32      https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
33
34  reg:
35    minItems: 1
36    items:
37      - description: SPI registers region
38      - description: Memory mapped flash region
39
40  interrupts:
41    maxItems: 1
42
43  clocks:
44    maxItems: 1
45
46    description:
47      Must reference the frequency given to the controller
48
49  sifive,fifo-depth:
50    description:
51      Depth of hardware queues; defaults to 8
52    $ref: "/schemas/types.yaml#/definitions/uint32"
53    enum: [8]
54    default: 8
55
56  sifive,max-bits-per-word:
57    description:
58      Maximum bits per word; defaults to 8
59    $ref: "/schemas/types.yaml#/definitions/uint32"
60    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
61    default: 8
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68
69examples:
70  - |
71    spi: spi@10040000 {
72      compatible = "sifive,fu540-c000-spi", "sifive,spi0";
73      reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
74      interrupt-parent = <&plic>;
75      interrupts = <51>;
76      clocks = <&tlclk>;
77      #address-cells = <1>;
78      #size-cells = <0>;
79      sifive,fifo-depth = <8>;
80      sifive,max-bits-per-word = <8>;
81    };
82
83...
84