1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Peripheral-specific properties for a SPI bus. 8 9description: 10 Many SPI controllers need to add properties to peripheral devices. They could 11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could 12 be controller specific like delay in clock or data lines, etc. These 13 properties need to be defined in the peripheral node because they are 14 per-peripheral and there can be multiple peripherals attached to a 15 controller. All those properties are listed here. The controller specific 16 properties should go in their own separate schema that should be referenced 17 from here. 18 19maintainers: 20 - Mark Brown <broonie@kernel.org> 21 22properties: 23 reg: 24 minItems: 1 25 maxItems: 256 26 items: 27 items: 28 - minimum: 0 29 maximum: 256 30 description: 31 Chip select used by the device. 32 33 spi-cs-high: 34 $ref: /schemas/types.yaml#/definitions/flag 35 description: 36 The device requires the chip select active high. 37 38 spi-lsb-first: 39 $ref: /schemas/types.yaml#/definitions/flag 40 description: 41 The device requires the LSB first mode. 42 43 spi-max-frequency: 44 $ref: /schemas/types.yaml#/definitions/uint32 45 description: 46 Maximum SPI clocking speed of the device in Hz. 47 48 spi-cs-setup-delay-ns: 49 description: 50 Delay in nanoseconds to be introduced by the controller after CS is 51 asserted. 52 53 spi-cs-hold-delay-ns: 54 description: 55 Delay in nanoseconds to be introduced by the controller before CS is 56 de-asserted. 57 58 spi-cs-inactive-delay-ns: 59 description: 60 Delay in nanoseconds to be introduced by the controller after CS is 61 de-asserted. 62 63 spi-rx-bus-width: 64 description: 65 Bus width to the SPI bus used for read transfers. 66 If 0 is provided, then no RX will be possible on this device. 67 68 Some SPI peripherals and controllers may have multiple data lanes for 69 receiving two or more words at the same time. If this is the case, each 70 index in the array represents the lane on both the SPI peripheral and 71 controller. Additional mapping properties may be needed if a lane is 72 skipped on either side. 73 $ref: /schemas/types.yaml#/definitions/uint32-array 74 items: 75 enum: [0, 1, 2, 4, 8] 76 default: [1] 77 78 spi-rx-lane-map: 79 description: Mapping of peripheral SDO lanes to controller SDI lanes. 80 Each index in the array represents a peripheral SDO lane, and the value 81 at that index represents the corresponding controller SDI lane. 82 $ref: /schemas/types.yaml#/definitions/uint32-array 83 default: [0, 1, 2, 3, 4, 5, 6, 7] 84 85 spi-rx-delay-us: 86 description: 87 Delay, in microseconds, after a read transfer. 88 89 rx-sample-delay-ns: 90 description: SPI Rx sample delay offset, unit is nanoseconds. 91 The delay from the default sample time before the actual 92 sample of the rxd input signal occurs. 93 94 spi-tx-bus-width: 95 description: 96 Bus width to the SPI bus used for write transfers. 97 If 0 is provided, then no TX will be possible on this device. 98 99 Some SPI peripherals and controllers may have multiple data lanes for 100 transmitting two or more words at the same time. If this is the case, each 101 index in the array represents the lane on both the SPI peripheral and 102 controller. Additional mapping properties may be needed if a lane is 103 skipped on either side. 104 $ref: /schemas/types.yaml#/definitions/uint32-array 105 items: 106 enum: [0, 1, 2, 4, 8] 107 default: [1] 108 109 spi-tx-lane-map: 110 description: Mapping of peripheral SDI lanes to controller SDO lanes. 111 Each index in the array represents a peripheral SDI lane, and the value 112 at that index represents the corresponding controller SDO lane. 113 $ref: /schemas/types.yaml#/definitions/uint32-array 114 default: [0, 1, 2, 3, 4, 5, 6, 7] 115 116 spi-tx-delay-us: 117 description: 118 Delay, in microseconds, after a write transfer. 119 120 stacked-memories: 121 description: Several SPI memories can be wired in stacked mode. 122 This basically means that either a device features several chip 123 selects, or that different devices must be seen as a single 124 bigger chip. This basically doubles (or more) the total address 125 space with only a single additional wire, while still needing 126 to repeat the commands when crossing a chip boundary. The size of 127 each chip should be provided as members of the array. 128 $ref: /schemas/types.yaml#/definitions/uint64-array 129 minItems: 2 130 maxItems: 4 131 132 parallel-memories: 133 description: Several SPI memories can be wired in parallel mode. 134 The devices are physically on a different buses but will always 135 act synchronously as each data word is spread across the 136 different memories (eg. even bits are stored in one memory, odd 137 bits in the other). This basically doubles the address space and 138 the throughput while greatly complexifying the wiring because as 139 many busses as devices must be wired. The size of each chip should 140 be provided as members of the array. 141 $ref: /schemas/types.yaml#/definitions/uint64-array 142 minItems: 2 143 maxItems: 4 144 145 st,spi-midi-ns: 146 deprecated: true 147 description: | 148 Only for STM32H7, (Master Inter-Data Idleness) minimum time 149 delay in nanoseconds inserted between two consecutive data frames. 150 151# The controller specific properties go here. 152allOf: 153 - $ref: arm,pl022-peripheral-props.yaml# 154 - $ref: cdns,qspi-nor-peripheral-props.yaml# 155 - $ref: fsl,dspi-peripheral-props.yaml# 156 - $ref: samsung,spi-peripheral-props.yaml# 157 - $ref: nvidia,tegra210-quad-peripheral-props.yaml# 158 159additionalProperties: true 160