xref: /linux/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml (revision 8e1bb4a41aa78d6105e59186af3dcd545fc66e70) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Peripheral-specific properties for a SPI bus.
8
9description:
10  Many SPI controllers need to add properties to peripheral devices. They could
11  be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12  controller specific like delay in clock or data lines, etc. These properties
13  need to be defined in the peripheral node because they are per-peripheral and
14  there can be multiple peripherals attached to a controller. All those
15  properties are listed here. The controller specific properties should go in
16  their own separate schema that should be referenced from here.
17
18maintainers:
19  - Mark Brown <broonie@kernel.org>
20
21properties:
22  reg:
23    minItems: 1
24    maxItems: 256
25    items:
26      items:
27        - minimum: 0
28          maximum: 256
29    description:
30      Chip select used by the device.
31
32  spi-cs-high:
33    $ref: /schemas/types.yaml#/definitions/flag
34    description:
35      The device requires the chip select active high.
36
37  spi-lsb-first:
38    $ref: /schemas/types.yaml#/definitions/flag
39    description:
40      The device requires the LSB first mode.
41
42  spi-max-frequency:
43    $ref: /schemas/types.yaml#/definitions/uint32
44    description:
45      Maximum SPI clocking speed of the device in Hz.
46
47  spi-cs-setup-delay-ns:
48    description:
49      Delay in nanoseconds to be introduced by the controller after CS is
50      asserted.
51
52  spi-cs-hold-delay-ns:
53    description:
54      Delay in nanoseconds to be introduced by the controller before CS is
55      de-asserted.
56
57  spi-cs-inactive-delay-ns:
58    description:
59      Delay in nanoseconds to be introduced by the controller after CS is
60      de-asserted.
61
62  spi-rx-bus-width:
63    description:
64      Bus width to the SPI bus used for read transfers.
65      If 0 is provided, then no RX will be possible on this device.
66    $ref: /schemas/types.yaml#/definitions/uint32
67    enum: [0, 1, 2, 4, 8]
68    default: 1
69
70  spi-rx-delay-us:
71    description:
72      Delay, in microseconds, after a read transfer.
73
74  rx-sample-delay-ns:
75    description: SPI Rx sample delay offset, unit is nanoseconds.
76      The delay from the default sample time before the actual
77      sample of the rxd input signal occurs.
78
79  spi-tx-bus-width:
80    description:
81      Bus width to the SPI bus used for write transfers.
82      If 0 is provided, then no TX will be possible on this device.
83    $ref: /schemas/types.yaml#/definitions/uint32
84    enum: [0, 1, 2, 4, 8]
85    default: 1
86
87  spi-tx-delay-us:
88    description:
89      Delay, in microseconds, after a write transfer.
90
91  stacked-memories:
92    description: Several SPI memories can be wired in stacked mode.
93      This basically means that either a device features several chip
94      selects, or that different devices must be seen as a single
95      bigger chip. This basically doubles (or more) the total address
96      space with only a single additional wire, while still needing
97      to repeat the commands when crossing a chip boundary. The size of
98      each chip should be provided as members of the array.
99    $ref: /schemas/types.yaml#/definitions/uint64-array
100    minItems: 2
101    maxItems: 4
102
103  parallel-memories:
104    description: Several SPI memories can be wired in parallel mode.
105      The devices are physically on a different buses but will always
106      act synchronously as each data word is spread across the
107      different memories (eg. even bits are stored in one memory, odd
108      bits in the other). This basically doubles the address space and
109      the throughput while greatly complexifying the wiring because as
110      many busses as devices must be wired. The size of each chip should
111      be provided as members of the array.
112    $ref: /schemas/types.yaml#/definitions/uint64-array
113    minItems: 2
114    maxItems: 4
115
116  st,spi-midi-ns:
117    description: |
118      Only for STM32H7, (Master Inter-Data Idleness) minimum time
119      delay in nanoseconds inserted between two consecutive data frames.
120
121# The controller specific properties go here.
122allOf:
123  - $ref: arm,pl022-peripheral-props.yaml#
124  - $ref: cdns,qspi-nor-peripheral-props.yaml#
125  - $ref: fsl,dspi-peripheral-props.yaml#
126  - $ref: samsung,spi-peripheral-props.yaml#
127  - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
128
129additionalProperties: true
130