1Marvell Orion SPI device 2 3Required properties: 4- compatible : should be on of the following: 5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs 6 - "marvell,armada-370-spi", for the Armada 370 SoCs 7 - "marvell,armada-375-spi", for the Armada 375 SoCs 8 - "marvell,armada-380-spi", for the Armada 38x SoCs 9 - "marvell,armada-390-spi", for the Armada 39x SoCs 10 - "marvell,armada-xp-spi", for the Armada XP SoCs 11- reg : offset and length of the register set for the device. 12 This property can optionally have additional entries to configure 13 the SPI direct access mode that some of the Marvell SoCs support 14 additionally to the normal indirect access (PIO) mode. The values 15 for the MBus "target" and "attribute" are defined in the Marvell 16 SoC "Functional Specifications" Manual in the chapter "Marvell 17 Core Processor Address Decoding". 18 The eight register sets following the control registers refer to 19 chip-select lines 0 through 7 respectively. 20- cell-index : Which of multiple SPI controllers is this. 21Optional properties: 22- interrupts : Is currently not used. 23 24Example: 25 spi@10600 { 26 compatible = "marvell,orion-spi"; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 cell-index = <0>; 30 reg = <0x10600 0x28>; 31 interrupts = <23>; 32 status = "disabled"; 33 }; 34 35Example with SPI direct mode support (optionally): 36 spi0: spi@10600 { 37 compatible = "marvell,orion-spi"; 38 #address-cells = <1>; 39 #size-cells = <0>; 40 cell-index = <0>; 41 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */ 42 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */ 43 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */ 44 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */ 45 <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */ 46 <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */ 47 <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */ 48 <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */ 49 <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */ 50 interrupts = <23>; 51 status = "disabled"; 52 }; 53 54To enable the direct mode, the board specific 'ranges' property in the 55'soc' node needs to add the entries for the desired SPI controllers 56and its chip-selects that are used in the direct mode instead of PIO 57mode. Here an example for this (SPI controller 0, device 1 and SPI 58controller 1, device 2 are used in direct mode. All other SPI device 59are used in the default indirect (PIO) mode): 60 soc { 61 /* 62 * Enable the SPI direct access by configuring an entry 63 * here in the board-specific ranges property 64 */ 65 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */ 66 <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM */ 67 <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */ 68 <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>; /* SPI1-DEV2 */ 69 70For further information on the MBus bindings, please see the MBus 71DT documentation: 72Documentation/devicetree/bindings/bus/mvebu-mbus.txt 73