1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/samsung,spi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung S3C/S5P/Exynos SoC SPI controller 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 12description: 13 All the SPI controller nodes should be represented in the aliases node using 14 the following format 'spi{n}' where n is a unique number for the alias. 15 16properties: 17 compatible: 18 oneOf: 19 - enum: 20 - google,gs101-spi 21 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 22 - samsung,s3c6410-spi 23 - samsung,s5pv210-spi # for S5PV210 and S5PC110 24 - samsung,exynos4210-spi 25 - samsung,exynos5433-spi 26 - samsung,exynos850-spi 27 - samsung,exynosautov9-spi 28 - tesla,fsd-spi 29 - items: 30 - enum: 31 - samsung,exynos8895-spi 32 - const: samsung,exynos850-spi 33 - const: samsung,exynos7-spi 34 deprecated: true 35 36 clocks: 37 minItems: 2 38 maxItems: 3 39 40 clock-names: 41 minItems: 2 42 maxItems: 3 43 44 dmas: 45 minItems: 2 46 maxItems: 2 47 48 dma-names: 49 items: 50 - const: tx 51 - const: rx 52 53 interrupts: 54 maxItems: 1 55 56 no-cs-readback: 57 description: 58 The CS line is disconnected, therefore the device should not operate 59 based on CS signalling. 60 type: boolean 61 62 num-cs: 63 minimum: 1 64 maximum: 4 65 default: 1 66 67 samsung,spi-src-clk: 68 description: 69 If the spi controller includes a internal clock mux to select the clock 70 source for the spi bus clock, this property can be used to indicate the 71 clock to be used for driving the spi bus clock. If not specified, the 72 clock number 0 is used as default. 73 $ref: /schemas/types.yaml#/definitions/uint32 74 default: 0 75 76 reg: 77 maxItems: 1 78 79required: 80 - compatible 81 - clocks 82 - clock-names 83 - interrupts 84 - reg 85 86allOf: 87 - $ref: spi-controller.yaml# 88 - if: 89 properties: 90 compatible: 91 contains: 92 enum: 93 - samsung,exynos5433-spi 94 - samsung,exynosautov9-spi 95 then: 96 properties: 97 clocks: 98 minItems: 3 99 maxItems: 3 100 clock-names: 101 items: 102 - const: spi 103 - enum: 104 - spi_busclk0 105 - spi_busclk1 106 - spi_busclk2 107 - spi_busclk3 108 - const: spi_ioclk 109 else: 110 properties: 111 clocks: 112 minItems: 2 113 maxItems: 2 114 clock-names: 115 items: 116 - const: spi 117 - enum: 118 - spi_busclk0 119 - spi_busclk1 120 - spi_busclk2 121 - spi_busclk3 122 123unevaluatedProperties: false 124 125examples: 126 - | 127 #include <dt-bindings/clock/exynos5433.h> 128 #include <dt-bindings/clock/samsung,s2mps11.h> 129 #include <dt-bindings/interrupt-controller/arm-gic.h> 130 #include <dt-bindings/gpio/gpio.h> 131 132 spi@14d30000 { 133 compatible = "samsung,exynos5433-spi"; 134 reg = <0x14d30000 0x100>; 135 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 136 dmas = <&pdma0 11>, <&pdma0 10>; 137 dma-names = "tx", "rx"; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 clocks = <&cmu_peric CLK_PCLK_SPI1>, 141 <&cmu_peric CLK_SCLK_SPI1>, 142 <&cmu_peric CLK_SCLK_IOCLK_SPI1>; 143 clock-names = "spi", 144 "spi_busclk0", 145 "spi_ioclk"; 146 samsung,spi-src-clk = <0>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&spi1_bus>; 149 num-cs = <1>; 150 151 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; 152 153 audio-codec@0 { 154 compatible = "wlf,wm5110"; 155 reg = <0x0>; 156 spi-max-frequency = <20000000>; 157 interrupt-parent = <&gpa0>; 158 interrupts = <4 IRQ_TYPE_NONE>; 159 clocks = <&pmu_system_controller 0>, 160 <&s2mps13_osc S2MPS11_CLK_BT>; 161 clock-names = "mclk1", "mclk2"; 162 163 gpio-controller; 164 #gpio-cells = <2>; 165 interrupt-controller; 166 #interrupt-cells = <2>; 167 168 wlf,micd-detect-debounce = <300>; 169 wlf,micd-bias-start-time = <0x1>; 170 wlf,micd-rate = <0x7>; 171 wlf,micd-dbtime = <0x2>; 172 wlf,micd-force-micbias; 173 wlf,micd-configs = <0x0 1 0>; 174 wlf,hpdet-channel = <1>; 175 wlf,gpsw = <0x1>; 176 wlf,inmode = <2 0 2 0>; 177 178 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>; 179 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>; 180 181 /* core supplies */ 182 AVDD-supply = <&ldo18_reg>; 183 DBVDD1-supply = <&ldo18_reg>; 184 CPVDD-supply = <&ldo18_reg>; 185 DBVDD2-supply = <&ldo18_reg>; 186 DBVDD3-supply = <&ldo18_reg>; 187 SPKVDDL-supply = <&ldo18_reg>; 188 SPKVDDR-supply = <&ldo18_reg>; 189 190 controller-data { 191 samsung,spi-feedback-delay = <0>; 192 }; 193 }; 194 }; 195