1*8c87a46eSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*8c87a46eSThierry Reding%YAML 1.2 3*8c87a46eSThierry Reding--- 4*8c87a46eSThierry Reding$id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml# 5*8c87a46eSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6*8c87a46eSThierry Reding 7*8c87a46eSThierry Redingtitle: NVIDIA Tegra20/30 SLINK controller 8*8c87a46eSThierry Reding 9*8c87a46eSThierry Redingmaintainers: 10*8c87a46eSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11*8c87a46eSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12*8c87a46eSThierry Reding 13*8c87a46eSThierry Redingproperties: 14*8c87a46eSThierry Reding compatible: 15*8c87a46eSThierry Reding enum: 16*8c87a46eSThierry Reding - nvidia,tegra20-slink 17*8c87a46eSThierry Reding - nvidia,tegra30-slink 18*8c87a46eSThierry Reding 19*8c87a46eSThierry Reding reg: 20*8c87a46eSThierry Reding maxItems: 1 21*8c87a46eSThierry Reding 22*8c87a46eSThierry Reding interrupts: 23*8c87a46eSThierry Reding maxItems: 1 24*8c87a46eSThierry Reding 25*8c87a46eSThierry Reding clocks: 26*8c87a46eSThierry Reding items: 27*8c87a46eSThierry Reding - description: module clock 28*8c87a46eSThierry Reding 29*8c87a46eSThierry Reding resets: 30*8c87a46eSThierry Reding items: 31*8c87a46eSThierry Reding - description: module reset 32*8c87a46eSThierry Reding 33*8c87a46eSThierry Reding reset-names: 34*8c87a46eSThierry Reding items: 35*8c87a46eSThierry Reding - const: spi 36*8c87a46eSThierry Reding 37*8c87a46eSThierry Reding dmas: 38*8c87a46eSThierry Reding items: 39*8c87a46eSThierry Reding - description: DMA channel used for reception 40*8c87a46eSThierry Reding - description: DMA channel used for transmission 41*8c87a46eSThierry Reding 42*8c87a46eSThierry Reding dma-names: 43*8c87a46eSThierry Reding items: 44*8c87a46eSThierry Reding - const: rx 45*8c87a46eSThierry Reding - const: tx 46*8c87a46eSThierry Reding 47*8c87a46eSThierry Reding operating-points-v2: 48*8c87a46eSThierry Reding $ref: /schemas/types.yaml#/definitions/phandle 49*8c87a46eSThierry Reding 50*8c87a46eSThierry Reding power-domains: 51*8c87a46eSThierry Reding items: 52*8c87a46eSThierry Reding - description: phandle to the core power domain 53*8c87a46eSThierry Reding 54*8c87a46eSThierry Reding spi-max-frequency: 55*8c87a46eSThierry Reding description: Maximum SPI clocking speed of the controller in Hz. 56*8c87a46eSThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 57*8c87a46eSThierry Reding 58*8c87a46eSThierry RedingallOf: 59*8c87a46eSThierry Reding - $ref: spi-controller.yaml 60*8c87a46eSThierry Reding 61*8c87a46eSThierry RedingunevaluatedProperties: false 62*8c87a46eSThierry Reding 63*8c87a46eSThierry Redingrequired: 64*8c87a46eSThierry Reding - compatible 65*8c87a46eSThierry Reding - reg 66*8c87a46eSThierry Reding - interrupts 67*8c87a46eSThierry Reding - clocks 68*8c87a46eSThierry Reding - resets 69*8c87a46eSThierry Reding - reset-names 70*8c87a46eSThierry Reding - dmas 71*8c87a46eSThierry Reding - dma-names 72*8c87a46eSThierry Reding 73*8c87a46eSThierry Redingexamples: 74*8c87a46eSThierry Reding - | 75*8c87a46eSThierry Reding #include <dt-bindings/clock/tegra20-car.h> 76*8c87a46eSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 77*8c87a46eSThierry Reding 78*8c87a46eSThierry Reding spi@7000d600 { 79*8c87a46eSThierry Reding compatible = "nvidia,tegra20-slink"; 80*8c87a46eSThierry Reding reg = <0x7000d600 0x200>; 81*8c87a46eSThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 82*8c87a46eSThierry Reding spi-max-frequency = <25000000>; 83*8c87a46eSThierry Reding #address-cells = <1>; 84*8c87a46eSThierry Reding #size-cells = <0>; 85*8c87a46eSThierry Reding clocks = <&tegra_car TEGRA20_CLK_SBC2>; 86*8c87a46eSThierry Reding resets = <&tegra_car 44>; 87*8c87a46eSThierry Reding reset-names = "spi"; 88*8c87a46eSThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 89*8c87a46eSThierry Reding dma-names = "rx", "tx"; 90*8c87a46eSThierry Reding }; 91