1*b8968c38SThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b8968c38SThierry Reding%YAML 1.2 3*b8968c38SThierry Reding--- 4*b8968c38SThierry Reding$id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml# 5*b8968c38SThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b8968c38SThierry Reding 7*b8968c38SThierry Redingtitle: NVIDIA Tegra114 SPI controller 8*b8968c38SThierry Reding 9*b8968c38SThierry Redingmaintainers: 10*b8968c38SThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11*b8968c38SThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12*b8968c38SThierry Reding 13*b8968c38SThierry Redingproperties: 14*b8968c38SThierry Reding compatible: 15*b8968c38SThierry Reding oneOf: 16*b8968c38SThierry Reding - const: nvidia,tegra114-spi 17*b8968c38SThierry Reding - items: 18*b8968c38SThierry Reding - enum: 19*b8968c38SThierry Reding - nvidia,tegra210-spi 20*b8968c38SThierry Reding - nvidia,tegra124-spi 21*b8968c38SThierry Reding - const: nvidia,tegra114-spi 22*b8968c38SThierry Reding 23*b8968c38SThierry Reding reg: 24*b8968c38SThierry Reding maxItems: 1 25*b8968c38SThierry Reding 26*b8968c38SThierry Reding interrupts: 27*b8968c38SThierry Reding maxItems: 1 28*b8968c38SThierry Reding 29*b8968c38SThierry Reding clocks: 30*b8968c38SThierry Reding items: 31*b8968c38SThierry Reding - description: SPI module clock 32*b8968c38SThierry Reding 33*b8968c38SThierry Reding clock-names: 34*b8968c38SThierry Reding items: 35*b8968c38SThierry Reding - const: spi 36*b8968c38SThierry Reding 37*b8968c38SThierry Reding resets: 38*b8968c38SThierry Reding items: 39*b8968c38SThierry Reding - description: SPI module reset 40*b8968c38SThierry Reding 41*b8968c38SThierry Reding reset-names: 42*b8968c38SThierry Reding items: 43*b8968c38SThierry Reding - const: spi 44*b8968c38SThierry Reding 45*b8968c38SThierry Reding dmas: 46*b8968c38SThierry Reding items: 47*b8968c38SThierry Reding - description: DMA channel for the reception FIFO 48*b8968c38SThierry Reding - description: DMA channel for the transmission FIFO 49*b8968c38SThierry Reding 50*b8968c38SThierry Reding dma-names: 51*b8968c38SThierry Reding items: 52*b8968c38SThierry Reding - const: rx 53*b8968c38SThierry Reding - const: tx 54*b8968c38SThierry Reding 55*b8968c38SThierry Reding spi-max-frequency: 56*b8968c38SThierry Reding description: Maximum SPI clocking speed of the controller in Hz. 57*b8968c38SThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 58*b8968c38SThierry Reding 59*b8968c38SThierry RedingallOf: 60*b8968c38SThierry Reding - $ref: spi-controller.yaml 61*b8968c38SThierry Reding 62*b8968c38SThierry RedingunevaluatedProperties: false 63*b8968c38SThierry Reding 64*b8968c38SThierry Redingrequired: 65*b8968c38SThierry Reding - compatible 66*b8968c38SThierry Reding - reg 67*b8968c38SThierry Reding - interrupts 68*b8968c38SThierry Reding - clocks 69*b8968c38SThierry Reding - clock-names 70*b8968c38SThierry Reding - resets 71*b8968c38SThierry Reding - reset-names 72*b8968c38SThierry Reding - dmas 73*b8968c38SThierry Reding - dma-names 74*b8968c38SThierry Reding 75*b8968c38SThierry Redingexamples: 76*b8968c38SThierry Reding - | 77*b8968c38SThierry Reding spi@7000d600 { 78*b8968c38SThierry Reding compatible = "nvidia,tegra114-spi"; 79*b8968c38SThierry Reding reg = <0x7000d600 0x200>; 80*b8968c38SThierry Reding interrupts = <0 82 0x04>; 81*b8968c38SThierry Reding clocks = <&tegra_car 44>; 82*b8968c38SThierry Reding clock-names = "spi"; 83*b8968c38SThierry Reding resets = <&tegra_car 44>; 84*b8968c38SThierry Reding reset-names = "spi"; 85*b8968c38SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 86*b8968c38SThierry Reding dma-names = "rx", "tx"; 87*b8968c38SThierry Reding 88*b8968c38SThierry Reding spi-max-frequency = <25000000>; 89*b8968c38SThierry Reding 90*b8968c38SThierry Reding #address-cells = <1>; 91*b8968c38SThierry Reding #size-cells = <0>; 92*b8968c38SThierry Reding 93*b8968c38SThierry Reding flash@0 { 94*b8968c38SThierry Reding compatible = "jedec,spi-nor"; 95*b8968c38SThierry Reding reg = <0>; 96*b8968c38SThierry Reding spi-max-frequency = <20000000>; 97*b8968c38SThierry Reding nvidia,rx-clk-tap-delay = <0>; 98*b8968c38SThierry Reding nvidia,tx-clk-tap-delay = <16>; 99*b8968c38SThierry Reding }; 100*b8968c38SThierry Reding }; 101