1* Nuvoton FLASH Interface Unit (FIU) SPI Controller 2 3NPCM FIU supports single, dual and quad communication interface. 4 5The NPCM7XX supports three FIU modules, 6FIU0 and FIUx supports two chip selects, 7FIU3 support four chip select. 8 9Required properties: 10 - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC 11 - #address-cells : should be 1. 12 - #size-cells : should be 0. 13 - reg : the first contains the register location and length, 14 the second contains the memory mapping address and length 15 - reg-names: Should contain the reg names "control" and "memory" 16 - clocks : phandle of FIU reference clock. 17 18Required properties in case the pins can be muxed: 19 - pinctrl-names : a pinctrl state named "default" must be defined. 20 - pinctrl-0 : phandle referencing pin configuration of the device. 21 22Optional property: 23 - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. 24 25Aliases: 26- All the FIU controller nodes should be represented in the aliases node using 27 the following format 'fiu{n}' where n is a unique number for the alias. 28 In the NPCM7XX BMC: 29 fiu0 represent fiu 0 controller 30 fiu1 represent fiu 3 controller 31 fiu2 represent fiu x controller 32 33Example: 34fiu3: spi@c00000000 { 35 compatible = "nuvoton,npcm750-fiu"; 36 #address-cells = <1>; 37 #size-cells = <0>; 38 reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; 39 reg-names = "control", "memory"; 40 clocks = <&clk NPCM7XX_CLK_AHB>; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&spi3_pins>; 43 spi-nor@0 { 44 ... 45 }; 46}; 47 48