1* SPI (Serial Peripheral Interface) 2 3Required properties: 4- cell-index : QE SPI subblock index. 5 0: QE subblock SPI1 6 1: QE subblock SPI2 7- compatible : should be "fsl,spi". 8- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 9- reg : Offset and length of the register set for the device 10- interrupts : <a b> where a is the interrupt number and b is a 11 field that represents an encoding of the sense and level 12 information for the interrupt. This should be encoded based on 13 the information in section 2) depending on the type of interrupt 14 controller you have. 15- interrupt-parent : the phandle for the interrupt controller that 16 services interrupts for this device. 17- clock-frequency : input clock frequency to non FSL_SOC cores 18 19Optional properties: 20- gpios : specifies the gpio pins to be used for chipselects. 21 The gpios will be referred to as reg = <index> in the SPI child nodes. 22 If unspecified, a single SPI device without a chip select can be used. 23 24Example: 25 spi@4c0 { 26 cell-index = <0>; 27 compatible = "fsl,spi"; 28 reg = <4c0 40>; 29 interrupts = <82 0>; 30 interrupt-parent = <700>; 31 mode = "cpu"; 32 gpios = <&gpio 18 1 // device reg=<0> 33 &gpio 19 1>; // device reg=<1> 34 }; 35 36 37* eSPI (Enhanced Serial Peripheral Interface) 38 39Required properties: 40- compatible : should be "fsl,mpc8536-espi". 41- reg : Offset and length of the register set for the device. 42- interrupts : should contain eSPI interrupt, the device has one interrupt. 43- fsl,espi-num-chipselects : the number of the chipselect signals. 44 45Example: 46 spi@110000 { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 compatible = "fsl,mpc8536-espi"; 50 reg = <0x110000 0x1000>; 51 interrupts = <53 0x2>; 52 interrupt-parent = <&mpic>; 53 fsl,espi-num-chipselects = <4>; 54 }; 55