1d524dac9SGrant Likely* SPI (Serial Peripheral Interface) 2d524dac9SGrant Likely 3d524dac9SGrant LikelyRequired properties: 4d524dac9SGrant Likely- cell-index : QE SPI subblock index. 5d524dac9SGrant Likely 0: QE subblock SPI1 6d524dac9SGrant Likely 1: QE subblock SPI2 7447b0c7bSAndreas Larsson- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". 8d524dac9SGrant Likely- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 9d524dac9SGrant Likely- reg : Offset and length of the register set for the device 10d524dac9SGrant Likely- interrupts : <a b> where a is the interrupt number and b is a 11d524dac9SGrant Likely field that represents an encoding of the sense and level 12d524dac9SGrant Likely information for the interrupt. This should be encoded based on 13d524dac9SGrant Likely the information in section 2) depending on the type of interrupt 14d524dac9SGrant Likely controller you have. 15e8beacbbSAndreas Larsson- clock-frequency : input clock frequency to non FSL_SOC cores 16d524dac9SGrant Likely 17d524dac9SGrant LikelyOptional properties: 18*8c452a88SChristophe Leroy- cs-gpios : specifies the gpio pins to be used for chipselects. 19d524dac9SGrant Likely The gpios will be referred to as reg = <index> in the SPI child nodes. 20d524dac9SGrant Likely If unspecified, a single SPI device without a chip select can be used. 2169b921acSRasmus Villemoes- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the 2269b921acSRasmus Villemoes SPISEL_BOOT signal is used as chip select for a slave device. Use 2369b921acSRasmus Villemoes reg = <number of gpios> in the corresponding child node, i.e. 0 if 24*8c452a88SChristophe Leroy the cs-gpios property is not present. 25d524dac9SGrant Likely 26d524dac9SGrant LikelyExample: 27d524dac9SGrant Likely spi@4c0 { 28d524dac9SGrant Likely cell-index = <0>; 29d524dac9SGrant Likely compatible = "fsl,spi"; 30d524dac9SGrant Likely reg = <4c0 40>; 31d524dac9SGrant Likely interrupts = <82 0>; 32d524dac9SGrant Likely interrupt-parent = <700>; 33d524dac9SGrant Likely mode = "cpu"; 34*8c452a88SChristophe Leroy cs-gpios = <&gpio 18 1 // device reg=<0> 35d524dac9SGrant Likely &gpio 19 1>; // device reg=<1> 36d524dac9SGrant Likely }; 37d524dac9SGrant Likely 38d524dac9SGrant Likely 39d524dac9SGrant Likely* eSPI (Enhanced Serial Peripheral Interface) 40d524dac9SGrant Likely 41d524dac9SGrant LikelyRequired properties: 42d524dac9SGrant Likely- compatible : should be "fsl,mpc8536-espi". 43d524dac9SGrant Likely- reg : Offset and length of the register set for the device. 44d524dac9SGrant Likely- interrupts : should contain eSPI interrupt, the device has one interrupt. 45d524dac9SGrant Likely- fsl,espi-num-chipselects : the number of the chipselect signals. 46d524dac9SGrant Likely 47d0fb47a5SJane WanOptional properties: 48d0fb47a5SJane Wan- fsl,csbef: chip select assertion time in bits before frame starts 49d0fb47a5SJane Wan- fsl,csaft: chip select negation time in bits after frame ends 50d0fb47a5SJane Wan 51d524dac9SGrant LikelyExample: 52d524dac9SGrant Likely spi@110000 { 53d524dac9SGrant Likely #address-cells = <1>; 54d524dac9SGrant Likely #size-cells = <0>; 55d524dac9SGrant Likely compatible = "fsl,mpc8536-espi"; 56d524dac9SGrant Likely reg = <0x110000 0x1000>; 57d524dac9SGrant Likely interrupts = <53 0x2>; 58d524dac9SGrant Likely interrupt-parent = <&mpic>; 59d524dac9SGrant Likely fsl,espi-num-chipselects = <4>; 60d0fb47a5SJane Wan fsl,csbef = <1>; 61d0fb47a5SJane Wan fsl,csaft = <1>; 62d524dac9SGrant Likely }; 63