1*f3bfa0f0SJ. Neuschäfer# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f3bfa0f0SJ. Neuschäfer%YAML 1.2 3*f3bfa0f0SJ. Neuschäfer--- 4*f3bfa0f0SJ. Neuschäfer$id: http://devicetree.org/schemas/spi/fsl,spi.yaml# 5*f3bfa0f0SJ. Neuschäfer$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f3bfa0f0SJ. Neuschäfer 7*f3bfa0f0SJ. Neuschäfertitle: Freescale SPI (Serial Peripheral Interface) controller 8*f3bfa0f0SJ. Neuschäfer 9*f3bfa0f0SJ. Neuschäfermaintainers: 10*f3bfa0f0SJ. Neuschäfer - J. Neuschäfer <j.ne@posteo.net> 11*f3bfa0f0SJ. Neuschäfer 12*f3bfa0f0SJ. Neuschäferproperties: 13*f3bfa0f0SJ. Neuschäfer compatible: 14*f3bfa0f0SJ. Neuschäfer enum: 15*f3bfa0f0SJ. Neuschäfer - fsl,spi 16*f3bfa0f0SJ. Neuschäfer - aeroflexgaisler,spictrl 17*f3bfa0f0SJ. Neuschäfer 18*f3bfa0f0SJ. Neuschäfer reg: 19*f3bfa0f0SJ. Neuschäfer maxItems: 1 20*f3bfa0f0SJ. Neuschäfer 21*f3bfa0f0SJ. Neuschäfer cell-index: 22*f3bfa0f0SJ. Neuschäfer $ref: /schemas/types.yaml#/definitions/uint32 23*f3bfa0f0SJ. Neuschäfer description: | 24*f3bfa0f0SJ. Neuschäfer QE SPI subblock index. 25*f3bfa0f0SJ. Neuschäfer 0: QE subblock SPI1 26*f3bfa0f0SJ. Neuschäfer 1: QE subblock SPI2 27*f3bfa0f0SJ. Neuschäfer 28*f3bfa0f0SJ. Neuschäfer mode: 29*f3bfa0f0SJ. Neuschäfer description: SPI operation mode 30*f3bfa0f0SJ. Neuschäfer enum: 31*f3bfa0f0SJ. Neuschäfer - cpu 32*f3bfa0f0SJ. Neuschäfer - cpu-qe 33*f3bfa0f0SJ. Neuschäfer 34*f3bfa0f0SJ. Neuschäfer interrupts: 35*f3bfa0f0SJ. Neuschäfer maxItems: 1 36*f3bfa0f0SJ. Neuschäfer 37*f3bfa0f0SJ. Neuschäfer clock-frequency: 38*f3bfa0f0SJ. Neuschäfer description: input clock frequency to non FSL_SOC cores 39*f3bfa0f0SJ. Neuschäfer 40*f3bfa0f0SJ. Neuschäfer cs-gpios: true 41*f3bfa0f0SJ. Neuschäfer 42*f3bfa0f0SJ. Neuschäfer fsl,spisel_boot: 43*f3bfa0f0SJ. Neuschäfer $ref: /schemas/types.yaml#/definitions/flag 44*f3bfa0f0SJ. Neuschäfer description: 45*f3bfa0f0SJ. Neuschäfer For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used 46*f3bfa0f0SJ. Neuschäfer as chip select for a slave device. Use reg = <number of gpios> in the 47*f3bfa0f0SJ. Neuschäfer corresponding child node, i.e. 0 if the cs-gpios property is not present. 48*f3bfa0f0SJ. Neuschäfer 49*f3bfa0f0SJ. Neuschäferrequired: 50*f3bfa0f0SJ. Neuschäfer - compatible 51*f3bfa0f0SJ. Neuschäfer - reg 52*f3bfa0f0SJ. Neuschäfer - mode 53*f3bfa0f0SJ. Neuschäfer - interrupts 54*f3bfa0f0SJ. Neuschäfer 55*f3bfa0f0SJ. NeuschäferallOf: 56*f3bfa0f0SJ. Neuschäfer - $ref: spi-controller.yaml# 57*f3bfa0f0SJ. Neuschäfer 58*f3bfa0f0SJ. NeuschäferunevaluatedProperties: false 59*f3bfa0f0SJ. Neuschäfer 60*f3bfa0f0SJ. Neuschäferexamples: 61*f3bfa0f0SJ. Neuschäfer - | 62*f3bfa0f0SJ. Neuschäfer #include <dt-bindings/interrupt-controller/irq.h> 63*f3bfa0f0SJ. Neuschäfer 64*f3bfa0f0SJ. Neuschäfer spi@4c0 { 65*f3bfa0f0SJ. Neuschäfer compatible = "fsl,spi"; 66*f3bfa0f0SJ. Neuschäfer reg = <0x4c0 0x40>; 67*f3bfa0f0SJ. Neuschäfer cell-index = <0>; 68*f3bfa0f0SJ. Neuschäfer interrupts = <82 0>; 69*f3bfa0f0SJ. Neuschäfer mode = "cpu"; 70*f3bfa0f0SJ. Neuschäfer cs-gpios = <&gpio 18 IRQ_TYPE_EDGE_RISING // device reg=<0> 71*f3bfa0f0SJ. Neuschäfer &gpio 19 IRQ_TYPE_EDGE_RISING>; // device reg=<1> 72*f3bfa0f0SJ. Neuschäfer }; 73*f3bfa0f0SJ. Neuschäfer 74*f3bfa0f0SJ. Neuschäfer... 75