xref: /linux/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml (revision 5e3992fe72748ed3892be876f09d4d990548b7af) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence Quad SPI controller
8
9maintainers:
10  - Vaishnav Achath <vaishnav.a@ti.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: xlnx,versal-ospi-1.0
19    then:
20      required:
21        - power-domains
22  - if:
23      properties:
24        compatible:
25          contains:
26            const: starfive,jh7110-qspi
27    then:
28      properties:
29        resets:
30          minItems: 2
31          maxItems: 3
32
33        reset-names:
34          minItems: 2
35          maxItems: 3
36          items:
37            enum: [ qspi, qspi-ocp, rstc_ref ]
38
39    else:
40      properties:
41        resets:
42          maxItems: 2
43
44        reset-names:
45          minItems: 1
46          maxItems: 2
47          items:
48            enum: [ qspi, qspi-ocp ]
49
50properties:
51  compatible:
52    oneOf:
53      - items:
54          - enum:
55              - ti,k2g-qspi
56              - ti,am654-ospi
57              - intel,lgm-qspi
58              - xlnx,versal-ospi-1.0
59              - intel,socfpga-qspi
60              - starfive,jh7110-qspi
61          - const: cdns,qspi-nor
62      - const: cdns,qspi-nor
63
64  reg:
65    items:
66      - description: the controller register set
67      - description: the controller data area
68
69  interrupts:
70    maxItems: 1
71
72  clocks:
73    maxItems: 1
74
75  cdns,fifo-depth:
76    description:
77      Size of the data FIFO in words.
78    $ref: /schemas/types.yaml#/definitions/uint32
79    enum: [ 128, 256 ]
80    default: 128
81
82  cdns,fifo-width:
83    $ref: /schemas/types.yaml#/definitions/uint32
84    description:
85      Bus width of the data FIFO in bytes.
86    default: 4
87
88  cdns,trigger-address:
89    $ref: /schemas/types.yaml#/definitions/uint32
90    description:
91      32-bit indirect AHB trigger address.
92
93  cdns,is-decoded-cs:
94    type: boolean
95    description:
96      Flag to indicate whether decoder is used to select different chip select
97      for different memory regions.
98
99  cdns,rclk-en:
100    type: boolean
101    description:
102      Flag to indicate that QSPI return clock is used to latch the read
103      data rather than the QSPI clock. Make sure that QSPI return clock
104      is populated on the board before using this property.
105
106  power-domains:
107    maxItems: 1
108
109  resets:
110    minItems: 2
111    maxItems: 3
112
113  reset-names:
114    minItems: 2
115    maxItems: 3
116    items:
117      enum: [ qspi, qspi-ocp, rstc_ref ]
118
119required:
120  - compatible
121  - reg
122  - interrupts
123  - clocks
124  - cdns,fifo-depth
125  - cdns,fifo-width
126  - cdns,trigger-address
127  - '#address-cells'
128  - '#size-cells'
129
130unevaluatedProperties: false
131
132examples:
133  - |
134    qspi: spi@ff705000 {
135        compatible = "cdns,qspi-nor";
136        #address-cells = <1>;
137        #size-cells = <0>;
138        reg = <0xff705000 0x1000>,
139              <0xffa00000 0x1000>;
140        interrupts = <0 151 4>;
141        clocks = <&qspi_clk>;
142        cdns,fifo-depth = <128>;
143        cdns,fifo-width = <4>;
144        cdns,trigger-address = <0x00000000>;
145        resets = <&rst 0x1>, <&rst 0x2>;
146        reset-names = "qspi", "qspi-ocp";
147
148        flash@0 {
149            compatible = "jedec,spi-nor";
150            reg = <0x0>;
151        };
152    };
153