xref: /linux/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml (revision 30bbcb44707a97fcb62246bebc8b413b5ab293f8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Atmel SPI device
9
10maintainers:
11  - Tudor Ambarus <tudor.ambarus@linaro.org>
12
13allOf:
14  - $ref: spi-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: atmel,at91rm9200-spi
20      - items:
21          - enum:
22              - microchip,sam9x60-spi
23              - microchip,sam9x7-spi
24              - microchip,sama7d65-spi
25          - const: atmel,at91rm9200-spi
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clock-names:
34    items:
35      - const: spi_clk
36      - const: spi_gclk
37    minItems: 1
38
39  clocks:
40    items:
41      - description: Peripheral Bus clock
42      - description: Programmable Generic clock
43    minItems: 1
44
45  dmas:
46    items:
47      - description: TX DMA Channel
48      - description: RX DMA Channel
49
50  dma-names:
51    items:
52      - const: tx
53      - const: rx
54
55  atmel,fifo-size:
56    $ref: /schemas/types.yaml#/definitions/uint32
57    description: |
58      Maximum number of data the RX and TX FIFOs can store for FIFO
59      capable SPI controllers.
60    enum: [ 16, 32 ]
61
62required:
63  - compatible
64  - reg
65  - interrupts
66  - clock-names
67  - clocks
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/gpio/gpio.h>
74    #include <dt-bindings/interrupt-controller/irq.h>
75
76    spi1: spi@fffcc000 {
77        compatible = "atmel,at91rm9200-spi";
78        reg = <0xfffcc000 0x4000>;
79        interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
80        #address-cells = <1>;
81        #size-cells = <0>;
82        clocks = <&spi1_clk>;
83        clock-names = "spi_clk";
84        cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
85        atmel,fifo-size = <32>;
86
87        mmc@0 {
88            compatible = "mmc-spi-slot";
89            reg = <0>;
90            gpios = <&pioC 4 GPIO_ACTIVE_HIGH>;    /* CD */
91            spi-max-frequency = <25000000>;
92        };
93    };
94