1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2025 Amlogic, Inc. All rights reserved 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: SPI flash controller for Amlogic ARM SoCs 9 10maintainers: 11 - Liang Yang <liang.yang@amlogic.com> 12 - Feng Chen <feng.chen@amlogic.com> 13 - Xianwei Zhao <xianwei.zhao@amlogic.com> 14 15description: 16 The Amlogic SPI flash controller is an extended version of the Amlogic NAND 17 flash controller. It supports SPI Nor Flash and SPI NAND Flash(where the Host 18 ECC HW engine could be enabled). 19 20allOf: 21 - $ref: /schemas/spi/spi-controller.yaml# 22 23properties: 24 compatible: 25 const: amlogic,a4-spifc 26 27 reg: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: clock apb gate 33 - description: clock used for the controller 34 35 clock-names: 36 items: 37 - const: gate 38 - const: core 39 40 interrupts: 41 maxItems: 1 42 43 amlogic,rx-adj: 44 description: 45 Number of clock cycles by which sampling is delayed. 46 $ref: /schemas/types.yaml#/definitions/uint32 47 enum: [0, 1, 2, 3] 48 default: 0 49 50required: 51 - compatible 52 - reg 53 - clocks 54 - clock-names 55 56unevaluatedProperties: false 57 58examples: 59 - | 60 sfc0: spi@fe08d000 { 61 compatible = "amlogic,a4-spifc"; 62 reg = <0xfe08d000 0x800>; 63 clocks = <&clkc_periphs 31>, 64 <&clkc_periphs 102>; 65 clock-names = "gate", "core"; 66 67 pinctrl-0 = <&spiflash_default>; 68 pinctrl-names = "default"; 69 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 flash@0 { 74 compatible = "spi-nand"; 75 reg = <0>; 76 #address-cells = <1>; 77 #size-cells = <1>; 78 nand-ecc-engine = <&sfc0>; 79 nand-ecc-strength = <8>; 80 nand-ecc-step-size = <512>; 81 }; 82 }; 83