xref: /linux/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Analog Devices AXI SPI Engine Controller
8
9description: |
10  The AXI SPI Engine controller is part of the SPI Engine framework[1] and
11  allows memory mapped access to the SPI Engine control bus. This allows it
12  to be used as a general purpose software driven SPI controller as well as
13  some optional advanced acceleration and offloading capabilities.
14
15  [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine
16
17maintainers:
18  - Michael Hennerich <Michael.Hennerich@analog.com>
19  - Nuno Sá <nuno.sa@analog.com>
20
21allOf:
22  - $ref: /schemas/spi/spi-controller.yaml#
23
24properties:
25  compatible:
26    const: adi,axi-spi-engine-1.00.a
27
28  reg:
29    maxItems: 1
30
31  interrupts:
32    maxItems: 1
33
34  clocks:
35    items:
36      - description: The AXI interconnect clock.
37      - description: The SPI controller clock.
38
39  clock-names:
40    items:
41      - const: s_axi_aclk
42      - const: spi_clk
43
44required:
45  - compatible
46  - reg
47  - interrupts
48  - clocks
49  - clock-names
50
51unevaluatedProperties: false
52
53examples:
54  - |
55    spi@44a00000 {
56        compatible = "adi,axi-spi-engine-1.00.a";
57        reg = <0x44a00000 0x1000>;
58        interrupts = <0 56 4>;
59        clocks = <&clkc 15>, <&clkc 15>;
60        clock-names = "s_axi_aclk", "spi_clk";
61
62        #address-cells = <1>;
63        #size-cells = <0>;
64
65        /* SPI devices */
66    };
67