1*2f00f771SMaruthi Srinivas BayyavarapuDevice-Tree bindings for Xilinx SPDIF IP 2*2f00f771SMaruthi Srinivas Bayyavarapu 3*2f00f771SMaruthi Srinivas BayyavarapuThe IP supports playback and capture of SPDIF audio 4*2f00f771SMaruthi Srinivas Bayyavarapu 5*2f00f771SMaruthi Srinivas BayyavarapuRequired properties: 6*2f00f771SMaruthi Srinivas Bayyavarapu - compatible: "xlnx,spdif-2.0" 7*2f00f771SMaruthi Srinivas Bayyavarapu - clock-names: List of input clocks. 8*2f00f771SMaruthi Srinivas Bayyavarapu Required elements: "s_axi_aclk", "aud_clk_i" 9*2f00f771SMaruthi Srinivas Bayyavarapu - clocks: Input clock specifier. Refer to common clock bindings. 10*2f00f771SMaruthi Srinivas Bayyavarapu - reg: Base address and address length of the IP core instance. 11*2f00f771SMaruthi Srinivas Bayyavarapu - interrupts-parent: Phandle for interrupt controller. 12*2f00f771SMaruthi Srinivas Bayyavarapu - interrupts: List of Interrupt numbers. 13*2f00f771SMaruthi Srinivas Bayyavarapu - xlnx,spdif-mode: 0 :- receiver mode 14*2f00f771SMaruthi Srinivas Bayyavarapu 1 :- transmitter mode 15*2f00f771SMaruthi Srinivas Bayyavarapu - xlnx,aud_clk_i: input audio clock value. 16*2f00f771SMaruthi Srinivas Bayyavarapu 17*2f00f771SMaruthi Srinivas BayyavarapuExample: 18*2f00f771SMaruthi Srinivas Bayyavarapu spdif_0: spdif@80010000 { 19*2f00f771SMaruthi Srinivas Bayyavarapu clock-names = "aud_clk_i", "s_axi_aclk"; 20*2f00f771SMaruthi Srinivas Bayyavarapu clocks = <&misc_clk_0>, <&clk 71>; 21*2f00f771SMaruthi Srinivas Bayyavarapu compatible = "xlnx,spdif-2.0"; 22*2f00f771SMaruthi Srinivas Bayyavarapu interrupt-names = "spdif_interrupt"; 23*2f00f771SMaruthi Srinivas Bayyavarapu interrupt-parent = <&gic>; 24*2f00f771SMaruthi Srinivas Bayyavarapu interrupts = <0 91 4>; 25*2f00f771SMaruthi Srinivas Bayyavarapu reg = <0x0 0x80010000 0x0 0x10000>; 26*2f00f771SMaruthi Srinivas Bayyavarapu xlnx,spdif-mode = <1>; 27*2f00f771SMaruthi Srinivas Bayyavarapu xlnx,aud_clk_i = <49152913>; 28*2f00f771SMaruthi Srinivas Bayyavarapu }; 29