1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/ti,pcm512x.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: PCM512x and TAS575x audio CODECs/amplifiers 8 9maintainers: 10 - Animesh Agarwal <animeshagarwal28@gmail.com> 11 12allOf: 13 - $ref: dai-common.yaml# 14 15properties: 16 compatible: 17 enum: 18 - ti,pcm5121 19 - ti,pcm5122 20 - ti,pcm5141 21 - ti,pcm5142 22 - ti,pcm5242 23 - ti,tas5754 24 - ti,tas5756 25 26 reg: 27 maxItems: 1 28 29 AVDD-supply: true 30 31 DVDD-supply: true 32 33 CPVDD-supply: true 34 35 clocks: 36 maxItems: 1 37 description: A clock specifier for the clock connected as SCLK. If this is 38 absent the device will be configured to clock from BCLK. If pll-in and 39 pll-out are specified in addition to a clock, the device is configured to 40 accept clock input on a specified gpio pin. 41 42 '#sound-dai-cells': 43 const: 0 44 45 pll-in: 46 description: GPIO pin used to connect the pll using <1> through <6>. The 47 device will be configured for clock input on the given pll-in pin. 48 $ref: /schemas/types.yaml#/definitions/uint32 49 minimum: 1 50 maximum: 6 51 52 pll-out: 53 description: GPIO pin used to connect the pll using <1> through <6>. The 54 device will be configured for PLL output on the given pll-out pin. An 55 external connection from the pll-out pin to the SCLK pin is assumed. 56 $ref: /schemas/types.yaml#/definitions/uint32 57 minimum: 1 58 maximum: 6 59 60required: 61 - compatible 62 - reg 63 - AVDD-supply 64 - DVDD-supply 65 - CPVDD-supply 66 67if: 68 properties: 69 compatible: 70 contains: 71 enum: 72 - ti,tas5754 73 - ti,tas5756 74 75then: 76 properties: 77 pll-in: 78 maximum: 3 79 80 pll-out: 81 maximum: 3 82 83unevaluatedProperties: false 84 85examples: 86 - | 87 i2c { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 codec@4c { 91 compatible = "ti,pcm5142"; 92 reg = <0x4c>; 93 AVDD-supply = <®_3v3_analog>; 94 DVDD-supply = <®_1v8>; 95 CPVDD-supply = <®_3v3>; 96 #sound-dai-cells = <0>; 97 clocks = <&sck>; 98 pll-in = <3>; 99 pll-out = <6>; 100 }; 101 }; 102