xref: /linux/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml (revision 4359a011e259a4608afc7fb3635370c9d4ba5943) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - renesas,r9a07g043-ssi  # RZ/G2UL
17          - renesas,r9a07g044-ssi  # RZ/G2{L,LC}
18          - renesas,r9a07g054-ssi  # RZ/V2L
19      - const: renesas,rz-ssi
20
21  reg:
22    maxItems: 1
23
24  interrupts:
25    maxItems: 4
26
27  interrupt-names:
28    items:
29      - const: int_req
30      - const: dma_rx
31      - const: dma_tx
32      - const: dma_rt
33
34  clocks:
35    maxItems: 4
36
37  clock-names:
38    items:
39      - const: ssi
40      - const: ssi_sfr
41      - const: audio_clk1
42      - const: audio_clk2
43
44  power-domains:
45    maxItems: 1
46
47  resets:
48    maxItems: 1
49
50  dmas:
51    minItems: 1
52    maxItems: 2
53    description:
54      The first cell represents a phandle to dmac.
55      The second cell specifies the encoded MID/RID values of the SSI port
56      connected to the DMA client and the slave channel configuration
57      parameters.
58      bits[0:9]   - Specifies MID/RID value of a SSI channel as below
59                    MID/RID value of SSI rx0 = 0x256
60                    MID/RID value of SSI tx0 = 0x255
61                    MID/RID value of SSI rx1 = 0x25a
62                    MID/RID value of SSI tx1 = 0x259
63                    MID/RID value of SSI rt2 = 0x25f
64                    MID/RID value of SSI rx3 = 0x262
65                    MID/RID value of SSI tx3 = 0x261
66      bit[10]     - HIEN = 1, Detects a request in response to the rising edge
67                    of the signal
68      bit[11]     - LVL = 0, Detects based on the edge
69      bits[12:14] - AM = 2, Bus cycle mode
70      bit[15]     - TM = 0, Single transfer mode
71
72  dma-names:
73    oneOf:
74      - items:
75          - const: tx
76          - const: rx
77      - items:
78          - const: rt
79
80  '#sound-dai-cells':
81    const: 0
82
83required:
84  - compatible
85  - reg
86  - interrupts
87  - interrupt-names
88  - clocks
89  - clock-names
90  - resets
91  - '#sound-dai-cells'
92
93additionalProperties: false
94
95examples:
96  - |
97    #include <dt-bindings/interrupt-controller/arm-gic.h>
98    #include <dt-bindings/clock/r9a07g044-cpg.h>
99
100    ssi0: ssi@10049c00 {
101        compatible = "renesas,r9a07g044-ssi",
102                     "renesas,rz-ssi";
103            reg = <0x10049c00 0x400>;
104            interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
105                         <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
106                         <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
107                         <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
108            interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
109            clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
110                     <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
111                     <&audio_clk1>,
112                     <&audio_clk2>;
113            clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
114            power-domains = <&cpg>;
115            resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
116            dmas = <&dmac 0x2655>,
117                   <&dmac 0x2656>;
118            dma-names = "tx", "rx";
119            #sound-dai-cells = <0>;
120    };
121