1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Tegra210 ADMAIF 8 9description: | 10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel 11 that sends/receives data to/from AHUB must interface through an 12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF 13 Tx channel and ADMA channel receiving data from AHUB pairs with 14 ADMAIF Rx channel. 15 16maintainers: 17 - Jon Hunter <jonathanh@nvidia.com> 18 - Sameer Pujar <spujar@nvidia.com> 19 20properties: 21 $nodename: 22 pattern: "^admaif@[0-9a-f]*$" 23 24 compatible: 25 oneOf: 26 - enum: 27 - nvidia,tegra210-admaif 28 - nvidia,tegra186-admaif 29 - nvidia,tegra264-admaif 30 - items: 31 - enum: 32 - nvidia,tegra234-admaif 33 - nvidia,tegra194-admaif 34 - const: nvidia,tegra186-admaif 35 36 reg: 37 maxItems: 1 38 39 dmas: true 40 41 dma-names: true 42 43 interconnects: 44 items: 45 - description: APE read memory client 46 - description: APE write memory client 47 48 interconnect-names: 49 items: 50 - const: dma-mem # read 51 - const: write 52 53 iommus: 54 maxItems: 1 55 56 ports: 57 $ref: /schemas/graph.yaml#/properties/ports 58 description: | 59 Contains list of ACIF (Audio CIF) port nodes for ADMAIF channels. 60 The number of port nodes depends on the number of ADMAIF channels 61 that SoC may have. These are interfaced with respective ACIF ports 62 in AHUB (Audio Hub). Each port is capable of data transfers in 63 both directions. 64 65 patternProperties: 66 '^port@[0-9]': 67 $ref: audio-graph-port.yaml# 68 unevaluatedProperties: false 69 70if: 71 properties: 72 compatible: 73 contains: 74 const: nvidia,tegra210-admaif 75 76then: 77 properties: 78 dmas: 79 description: 80 DMA channel specifiers, equally divided for Tx and Rx. 81 minItems: 1 82 maxItems: 20 83 dma-names: 84 items: 85 pattern: "^[rt]x(10|[1-9])$" 86 description: 87 Should be "rx1", "rx2" ... "rx10" for DMA Rx channel 88 Should be "tx1", "tx2" ... "tx10" for DMA Tx channel 89 minItems: 1 90 maxItems: 20 91 interconnects: false 92 interconnect-names: false 93 iommus: false 94 95else: 96 properties: 97 dmas: 98 description: 99 DMA channel specifiers, equally divided for Tx and Rx. 100 minItems: 1 101 maxItems: 40 102 dma-names: 103 items: 104 pattern: "^[rt]x(1[0-9]|[1-9]|20)$" 105 description: 106 Should be "rx1", "rx2" ... "rx20" for DMA Rx channel 107 Should be "tx1", "tx2" ... "tx20" for DMA Tx channel 108 minItems: 1 109 maxItems: 40 110 111required: 112 - compatible 113 - reg 114 - dmas 115 - dma-names 116 117additionalProperties: false 118 119examples: 120 - | 121 admaif@702d0000 { 122 compatible = "nvidia,tegra210-admaif"; 123 reg = <0x702d0000 0x800>; 124 dmas = <&adma 1>, <&adma 1>, 125 <&adma 2>, <&adma 2>, 126 <&adma 3>, <&adma 3>, 127 <&adma 4>, <&adma 4>, 128 <&adma 5>, <&adma 5>, 129 <&adma 6>, <&adma 6>, 130 <&adma 7>, <&adma 7>, 131 <&adma 8>, <&adma 8>, 132 <&adma 9>, <&adma 9>, 133 <&adma 10>, <&adma 10>; 134 dma-names = "rx1", "tx1", 135 "rx2", "tx2", 136 "rx3", "tx3", 137 "rx4", "tx4", 138 "rx5", "tx5", 139 "rx6", "tx6", 140 "rx7", "tx7", 141 "rx8", "tx8", 142 "rx9", "tx9", 143 "rx10", "tx10"; 144 }; 145 146... 147