xref: /linux/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-sgtl5000.yaml (revision a4eb44a6435d6d8f9e642407a4a06f65eb90ca04) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-sgtl5000.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra audio complex with SGTL5000 CODEC
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13allOf:
14  - $ref: nvidia,tegra-audio-common.yaml#
15
16properties:
17  compatible:
18    items:
19      - pattern: '^[a-z0-9]+,tegra-audio-sgtl5000([-_][a-z0-9]+)+$'
20      - const: nvidia,tegra-audio-sgtl5000
21
22  nvidia,audio-routing:
23    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
24    description: |
25      A list of the connections between audio components.
26      Each entry is a pair of strings, the first being the connection's sink,
27      the second being the connection's source. Valid names for sources and
28      sinks are the pins (documented in the binding document),
29      and the jacks on the board.
30    minItems: 2
31    items:
32      enum:
33        # Board Connectors
34        - "Headphone Jack"
35        - "Line In Jack"
36        - "Mic Jack"
37
38        # CODEC Pins
39        - HP_OUT
40        - LINE_OUT
41        - LINE_IN
42        - MIC_IN
43
44required:
45  - nvidia,i2s-controller
46
47unevaluatedProperties: false
48
49examples:
50  - |
51    #include <dt-bindings/clock/tegra30-car.h>
52
53    sound {
54      compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
55                   "nvidia,tegra-audio-sgtl5000";
56      nvidia,model = "Toradex Apalis T30 SGTL5000";
57      nvidia,audio-routing =
58              "Headphone Jack", "HP_OUT",
59              "LINE_IN", "Line In Jack",
60              "MIC_IN", "Mic Jack";
61      nvidia,i2s-controller = <&tegra_i2s2>;
62      nvidia,audio-codec = <&codec>;
63      clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
64               <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
65               <&tegra_car TEGRA30_CLK_EXTERN1>;
66      clock-names = "pll_a", "pll_a_out0", "mclk";
67    };
68