xref: /linux/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml (revision 9270102a00aabbe4d1bbb6890d514b01f1c42989) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Audio Graph based Tegra sound card driver
8
9description: |
10  This is based on generic audio graph card driver along with additional
11  customizations for Tegra platforms. It uses the same bindings with
12  additional standard clock DT bindings required for Tegra.
13
14maintainers:
15  - Jon Hunter <jonathanh@nvidia.com>
16  - Sameer Pujar <spujar@nvidia.com>
17
18allOf:
19  - $ref: audio-graph.yaml#
20
21properties:
22  compatible:
23    enum:
24      - nvidia,tegra210-audio-graph-card
25      - nvidia,tegra186-audio-graph-card
26      - nvidia,tegra238-audio-graph-card
27      - nvidia,tegra264-audio-graph-card
28
29  clocks:
30    minItems: 2
31
32  clock-names:
33    items:
34      - const: pll_a
35      - const: plla_out0
36
37  assigned-clocks:
38    minItems: 1
39    maxItems: 3
40
41  assigned-clock-parents:
42    minItems: 1
43    maxItems: 3
44
45  assigned-clock-rates:
46    minItems: 1
47    maxItems: 3
48
49  interconnects:
50    items:
51      - description: APE read memory client
52      - description: APE write memory client
53
54  interconnect-names:
55    items:
56      - const: dma-mem # read
57      - const: write
58
59  iommus:
60    maxItems: 1
61
62required:
63  - clocks
64  - clock-names
65  - assigned-clocks
66  - assigned-clock-parents
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    #include<dt-bindings/clock/tegra210-car.h>
73
74    tegra_sound {
75        compatible = "nvidia,tegra210-audio-graph-card";
76
77        clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
78                 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
79        clock-names = "pll_a", "plla_out0";
80
81        assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
82                          <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
83                          <&tegra_car TEGRA210_CLK_EXTERN1>;
84        assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
85        assigned-clock-rates = <368640000>, <49152000>, <12288000>;
86
87        dais = /* FE */
88               <&admaif1_port>,
89               /* Router */
90               <&xbar_i2s1_port>,
91               /* I/O DAP Ports */
92               <&i2s1_port>;
93
94        label = "jetson-tx1-ape";
95    };
96
97    // The ports are defined for AHUB and its child devices.
98    ahub@702d0800 {
99        compatible = "nvidia,tegra210-ahub";
100        reg = <0x702d0800 0x800>;
101        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
102        clock-names = "ahub";
103        assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
104        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
105        #address-cells = <1>;
106        #size-cells = <1>;
107        ranges = <0x702d0000 0x702d0000 0x0000e400>;
108
109        ports {
110            #address-cells = <1>;
111            #size-cells = <0>;
112
113            port@0 {
114                reg = <0x0>;
115                xbar_admaif1_ep: endpoint {
116                    remote-endpoint = <&admaif1_ep>;
117                };
118            };
119
120            // ...
121
122            xbar_i2s1_port: port@a {
123                reg = <0xa>;
124                xbar_i2s1_ep: endpoint {
125                    remote-endpoint = <&i2s1_cif_ep>;
126                };
127            };
128        };
129
130        admaif@702d0000 {
131            compatible = "nvidia,tegra210-admaif";
132            reg = <0x702d0000 0x800>;
133            dmas = <&adma 1>,  <&adma 1>,
134                   <&adma 2>,  <&adma 2>,
135                   <&adma 3>,  <&adma 3>,
136                   <&adma 4>,  <&adma 4>,
137                   <&adma 5>,  <&adma 5>,
138                   <&adma 6>,  <&adma 6>,
139                   <&adma 7>,  <&adma 7>,
140                   <&adma 8>,  <&adma 8>,
141                   <&adma 9>,  <&adma 9>,
142                   <&adma 10>, <&adma 10>;
143            dma-names = "rx1",  "tx1",
144                        "rx2",  "tx2",
145                        "rx3",  "tx3",
146                        "rx4",  "tx4",
147                        "rx5",  "tx5",
148                        "rx6",  "tx6",
149                        "rx7",  "tx7",
150                        "rx8",  "tx8",
151                        "rx9",  "tx9",
152                        "rx10", "tx10";
153
154            ports {
155                #address-cells = <1>;
156                #size-cells = <0>;
157
158                admaif1_port: port@0 {
159                    reg = <0x0>;
160                    admaif1_ep: endpoint {
161                        remote-endpoint = <&xbar_admaif1_ep>;
162                    };
163                };
164
165                // More ADMAIF ports to follow
166            };
167        };
168
169        i2s@702d1000 {
170            compatible = "nvidia,tegra210-i2s";
171            clocks = <&tegra_car TEGRA210_CLK_I2S0>;
172            clock-names = "i2s";
173            assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
174            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
175            assigned-clock-rates = <1536000>;
176            reg = <0x702d1000 0x100>;
177
178            ports {
179                #address-cells = <1>;
180                #size-cells = <0>;
181
182                port@0 {
183                    reg = <0x0>;
184
185                    i2s1_cif_ep: endpoint {
186                        remote-endpoint = <&xbar_i2s1_ep>;
187                    };
188                };
189
190                i2s1_port: port@1 {
191                    reg = <0x1>;
192
193                    i2s1_dap: endpoint {
194                        dai-format = "i2s";
195                    };
196                };
197            };
198        };
199    };
200
201...
202