xref: /linux/Documentation/devicetree/bindings/sound/fsl,spdif.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
8
9maintainers:
10  - Shengjiu Wang <shengjiu.wang@nxp.com>
11
12description: |
13  The Freescale S/PDIF audio block is a stereo transceiver that allows the
14  processor to receive and transmit digital audio via an coaxial cable or
15  a fibre cable.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx35-spdif
21      - fsl,vf610-spdif
22      - fsl,imx6sx-spdif
23      - fsl,imx8qm-spdif
24      - fsl,imx8qxp-spdif
25      - fsl,imx8mq-spdif
26      - fsl,imx8mm-spdif
27      - fsl,imx8mn-spdif
28      - fsl,imx8ulp-spdif
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    minItems: 1
35    items:
36      - description: Combined or receive interrupt
37      - description: Transmit interrupt
38
39  dmas:
40    items:
41      - description: DMA controller phandle and request line for RX
42      - description: DMA controller phandle and request line for TX
43
44  dma-names:
45    items:
46      - const: rx
47      - const: tx
48
49  clocks:
50    items:
51      - description: The core clock of spdif controller.
52      - description: Clock for tx0 and rx0.
53      - description: Clock for tx1 and rx1.
54      - description: Clock for tx2 and rx2.
55      - description: Clock for tx3 and rx3.
56      - description: Clock for tx4 and rx4.
57      - description: Clock for tx5 and rx5.
58      - description: Clock for tx6 and rx6.
59      - description: Clock for tx7 and rx7.
60      - description: The spba clock is required when SPDIF is placed as a bus
61          slave of the Shared Peripheral Bus and when two or more bus masters
62          (CPU, DMA or DSP) try to access it. This property is optional depending
63          on the SoC design.
64      - description: PLL clock source for 8kHz series rate, optional.
65      - description: PLL clock source for 11khz series rate, optional.
66    minItems: 9
67
68  clock-names:
69    items:
70      - const: core
71      - const: rxtx0
72      - const: rxtx1
73      - const: rxtx2
74      - const: rxtx3
75      - const: rxtx4
76      - const: rxtx5
77      - const: rxtx6
78      - const: rxtx7
79      - const: spba
80      - const: pll8k
81      - const: pll11k
82    minItems: 9
83
84  big-endian:
85    $ref: /schemas/types.yaml#/definitions/flag
86    description: |
87      If this property is absent, the native endian mode will be in use
88      as default, or the big endian mode will be in use for all the device
89      registers. Set this flag for HCDs with big endian descriptors and big
90      endian registers.
91
92  power-domains:
93    maxItems: 1
94
95required:
96  - compatible
97  - reg
98  - interrupts
99  - dmas
100  - dma-names
101  - clocks
102  - clock-names
103
104additionalProperties: false
105
106allOf:
107  - if:
108      properties:
109        compatible:
110          enum:
111            - fsl,imx8qm-spdif
112            - fsl,imx8qxp-spdif
113    then:
114      properties:
115        interrupts:
116          minItems: 2
117    else:
118      properties:
119        interrupts:
120          maxItems: 1
121
122  - if:
123      properties:
124        compatible:
125          contains:
126            enum:
127              - fsl,imx8qm-spdif
128              - fsl,imx8qxp-spdif
129    then:
130      required:
131        - power-domains
132
133examples:
134  - |
135    spdif@2004000 {
136        compatible = "fsl,imx35-spdif";
137        reg = <0x02004000 0x4000>;
138        interrupts = <0 52 0x04>;
139        dmas = <&sdma 14 18 0>,
140               <&sdma 15 18 0>;
141        dma-names = "rx", "tx";
142        clocks = <&clks 197>, <&clks 3>,
143                 <&clks 197>, <&clks 107>,
144                 <&clks 0>, <&clks 118>,
145                 <&clks 62>, <&clks 139>,
146                 <&clks 0>;
147        clock-names = "core", "rxtx0",
148                      "rxtx1", "rxtx2",
149                      "rxtx3", "rxtx4",
150                      "rxtx5", "rxtx6",
151                      "rxtx7";
152        big-endian;
153    };
154