1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller 8 9maintainers: 10 - Shengjiu Wang <shengjiu.wang@nxp.com> 11 12description: | 13 The Freescale S/PDIF audio block is a stereo transceiver that allows the 14 processor to receive and transmit digital audio via an coaxial cable or 15 a fibre cable. 16 17properties: 18 compatible: 19 enum: 20 - fsl,imx35-spdif 21 - fsl,vf610-spdif 22 - fsl,imx6sx-spdif 23 - fsl,imx8qm-spdif 24 25 reg: 26 maxItems: 1 27 28 interrupts: 29 maxItems: 1 30 31 dmas: 32 items: 33 - description: DMA controller phandle and request line for RX 34 - description: DMA controller phandle and request line for TX 35 36 dma-names: 37 items: 38 - const: rx 39 - const: tx 40 41 clocks: 42 items: 43 - description: The core clock of spdif controller. 44 - description: Clock for tx0 and rx0. 45 - description: Clock for tx1 and rx1. 46 - description: Clock for tx2 and rx2. 47 - description: Clock for tx3 and rx3. 48 - description: Clock for tx4 and rx4. 49 - description: Clock for tx5 and rx5. 50 - description: Clock for tx6 and rx6. 51 - description: Clock for tx7 and rx7. 52 - description: The spba clock is required when SPDIF is placed as a bus 53 slave of the Shared Peripheral Bus and when two or more bus masters 54 (CPU, DMA or DSP) try to access it. This property is optional depending 55 on the SoC design. 56 minItems: 9 57 58 clock-names: 59 items: 60 - const: core 61 - const: rxtx0 62 - const: rxtx1 63 - const: rxtx2 64 - const: rxtx3 65 - const: rxtx4 66 - const: rxtx5 67 - const: rxtx6 68 - const: rxtx7 69 - const: spba 70 minItems: 9 71 72 big-endian: 73 $ref: /schemas/types.yaml#/definitions/flag 74 description: | 75 If this property is absent, the native endian mode will be in use 76 as default, or the big endian mode will be in use for all the device 77 registers. Set this flag for HCDs with big endian descriptors and big 78 endian registers. 79 80required: 81 - compatible 82 - reg 83 - interrupts 84 - dmas 85 - dma-names 86 - clocks 87 - clock-names 88 89additionalProperties: false 90 91examples: 92 - | 93 spdif@2004000 { 94 compatible = "fsl,imx35-spdif"; 95 reg = <0x02004000 0x4000>; 96 interrupts = <0 52 0x04>; 97 dmas = <&sdma 14 18 0>, 98 <&sdma 15 18 0>; 99 dma-names = "rx", "tx"; 100 clocks = <&clks 197>, <&clks 3>, 101 <&clks 197>, <&clks 107>, 102 <&clks 0>, <&clks 118>, 103 <&clks 62>, <&clks 139>, 104 <&clks 0>; 105 clock-names = "core", "rxtx0", 106 "rxtx1", "rxtx2", 107 "rxtx3", "rxtx4", 108 "rxtx5", "rxtx6", 109 "rxtx7"; 110 big-endian; 111 }; 112